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95f0cd5b6c
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Author SHA1 Message Date
gjz010
95f0cd5b6c Run cargo fmt. 2021-03-03 14:55:28 +08:00
gjz010
f68cd2486e Migrating to OpenSBI 0.9 with SBI spec 0.2 2021-03-03 14:32:41 +08:00
Chen
1ab076cfe9
Merge pull request #68 from equation314/rvm 
Hypervisor support using RVM
 2020-09-24 00:14:51 +08:00
Yuekai Jia
bc351b1c7f hypervisor: test hypervisor build in CI 2020-09-23 22:49:24 +08:00
Yuekai Jia
7973369b23 hypervisor: bump rcore-user version 2020-09-23 22:40:34 +08:00
Yuekai Jia
180e855ace hypervisor: import RVM 2020-09-20 23:30:28 +08:00
Chen
87e4039dd8
Merge pull request #66 from wfly1998/master 
update rboot; fix problem of sys_poll
 2020-08-25 09:51:10 +08:00
Yukiteru Lee
ec4871278d fix problem of sys_poll 2020-08-25 09:22:33 +08:00
Yukiteru Lee
341451c90b update rboot 2020-08-25 09:22:21 +08:00
Chen
d3ab8c58ad
Merge pull request #63 from rcore-os/fix-mipsel 
Fix mipsel
 2020-07-09 13:14:55 +08:00
Jiajie Chen
c31f76ffa4 Add mipsel back to github actions 2020-07-09 12:51:13 +08:00
Jiajie Chen
e601787ca2 Only yield for timer interrupt 2020-07-09 12:50:06 +08:00
Jiajie Chen
34e53e22b4 Fix mipsel serial 2020-07-09 12:40:50 +08:00
Jiajie Chen
8942bb8eeb Use uart16550 as serial in mipsel as well 2020-07-09 12:36:26 +08:00
刘丰源
6906337068 enable interrupt 2020-07-08 22:07:24 +08:00
Jiajie Chen
b13833e0e9 Implement wait_for_interrupt properly 2020-07-07 20:41:27 +08:00
Jiajie Chen
d0884a9019 Fix rdhwr simulation 2020-07-07 17:38:21 +08:00
Jiajie Chen
968361cc3e Enable cp1 in user mode 2020-07-07 17:31:04 +08:00
Jiajie Chen
85528673f1 Fix typo 2020-07-07 17:28:54 +08:00
Jiajie Chen
c170eb0414 Fix timer interrupt 2020-07-07 17:12:07 +08:00
Jiajie Chen
e554754e79 Fix mipsel syscall handling 2020-07-07 16:57:37 +08:00
Jiajie Chen
6a3a85ca5a Fix mipsel page fault handling 2020-07-07 15:49:55 +08:00
Jiajie Chen
4dd72365ca Fix mipsel context switch 2020-07-07 10:00:24 +08:00
Jiajie Chen
a16a9e238b Add IDE back for mips, remove mipssim 2020-07-07 08:25:30 +08:00
Jiajie Chen
100db70184 Fix compilation 2020-07-06 07:22:39 +08:00
Jiajie Chen
2589319769 Fix compilation for mipsel 2020-07-06 00:20:16 +08:00
Chen
455a29ba55
Merge pull request #62 from rcore-os/async 
Remove unused code, async-ify semaphore
 2020-06-30 17:50:13 +08:00
Jiajie Chen
93e946f900 Remove unused code, async-ify semaphore 2020-06-30 17:24:26 +08:00
Chen
e6e2f22955
Merge pull request #39 from rcore-os/pull-30-merge 
[Merge over master] Add support for mmap shared memory
 2020-06-30 14:54:45 +08:00
Jiajie Chen
4b68f69d79 Fix semid_ids layout 2020-06-30 14:49:50 +08:00
Jiajie Chen
7b9c85840e Implement IPC_SET for sem 2020-06-30 14:08:25 +08:00
Jiajie Chen
6a0e25431b Some code cleanup 2020-06-30 13:05:38 +08:00
Jiajie Chen
21f024c76d Remove non snake case names 2020-06-30 12:59:17 +08:00
Jiajie Chen
427a338095 Merge branch 'master' into pull-30-merge 2020-06-30 12:55:05 +08:00
Chen
723f3d7803
Merge pull request #61 from rcore-os/refactor 
Refactor
 2020-06-30 12:43:58 +08:00
Jiajie Chen
16eb1ed7e2 Move arch specific code to arch 2020-06-30 12:27:29 +08:00
Jiajie Chen
8822964045 Fix aarch64 compilation 2020-06-30 09:47:51 +08:00
Jiajie Chen
aa068944e2 Add rtc goldfish and dummy fp for riscv 2020-06-30 09:12:17 +08:00
Jiajie Chen
8823ba9034 Fix typo in last commit 2020-06-29 23:22:45 +08:00
Jiajie Chen
71015ef63c Setup x87 FPU control word correctly 2020-06-29 23:21:11 +08:00
Jiajie Chen
e32597ac82 Add fp save and restore and use accel=hvf in macOS 2020-06-29 22:53:30 +08:00
Jiajie Chen
34ca9963cb Fix signal masking 2020-06-29 20:48:42 +08:00
Jiajie Chen
8f0b2702f0 Get mcontext back for pthread_cancel 2020-06-29 12:03:29 +08:00
Jiajie Chen
7ba001a0fa Document and cleanup signal code 2020-06-29 11:49:03 +08:00
Jiajie Chen
68609a0f7c Add yield to avoid starvation 2020-06-29 11:09:21 +08:00
Jiajie Chen
bc525e1902 Cleanup signal code 2020-06-28 23:21:22 +08:00
Jiajie Chen
25382e211e Support signal in sleep 2020-06-28 22:21:52 +08:00
Jiajie Chen
5165269f4b Cleanup signal code and move sig alt stack to thread 2020-06-28 21:35:40 +08:00
Jiajie Chen
d33448b91e Ease riscv32/64 check, fix riscv32 2020-06-26 23:39:27 +08:00
Jiajie Chen
611aaa5f01 Update dependencies 2020-06-26 23:23:57 +08:00