Fix mipsel context switch

kernel/Cargo.lock

@@ -709,7 +709,7 @@ checksum = "3a385d94f3f62e60445a0adb9ff8d9621faa272234530d4c0f848ec98f88e316"
 [[package]]
 name = "trapframe"
 version = "0.4.3"
-source = "git+https://github.com/rcore-os/trapframe-rs?rev=e58d975#e58d9755f181de24431b5ff9437f396ac71e8429"
+source = "git+https://github.com/rcore-os/trapframe-rs?rev=e9a2164#e9a21646169f23934facdcf2299490732dbc6a7f"
 dependencies = [
  "raw-cpuid",
  "x86_64",

kernel/Cargo.toml

@@ -69,7 +69,7 @@ rcore-fs-devfs = { git = "https://github.com/rcore-os/rcore-fs", rev = "517af47"
 rlibc = "1.0"
 smoltcp = { git = "https://github.com/rcore-os/smoltcp", rev = "5bd87c7c", default-features = false, features = ["alloc", "log", "ethernet", "proto-ipv4", "proto-igmp", "socket-icmp", "socket-udp", "socket-tcp", "socket-raw"] }
 spin = "0.5"
-trapframe = { git = "https://github.com/rcore-os/trapframe-rs", rev = "e58d975" }
+trapframe = { git = "https://github.com/rcore-os/trapframe-rs", rev = "e9a2164" }
 virtio-drivers = { git = "https://github.com/rcore-os/virtio-drivers", rev = "dfa70e14" }
 volatile = "0.2"
 woke = "0.0.2"

kernel/build.rs

@@ -17,5 +17,11 @@ fn main() {
     } else if target.contains("riscv64") {
         println!("cargo:rustc-cfg=riscv");
         println!("cargo:rustc-cfg=riscv64");
+    } else if target.contains("mipsel") {
+        println!("cargo:rustc-cfg=mipsel");
+    } else if target.contains("aarch64") {
+        println!("cargo:rustc-cfg=aarch64");
+    } else if target.contains("x86_64") {
+        println!("cargo:rustc-cfg=x86_64");
     }
 }

kernel/src/arch/mipsel/board/malta/mod.rs

@@ -20,7 +20,7 @@ pub fn init_serial_early() {
     let mut status = cp0::status::read();
     status.enable_hard_int2();
     cp0::status::write(status);
-    println!("Hello QEMU Malta!");
+    info!("Hello QEMU Malta!");
 }
 
 /// Initialize other board drivers

kernel/src/arch/mipsel/interrupt/mod.rs

@@ -11,12 +11,9 @@ pub mod consts;
 
 /// Initialize interrupt
 pub fn init() {
-    extern "C" {
-        fn trap_entry();
+    unsafe {
+        trapframe::init();
     }
-    // Set the exception vector address
-    cp0::ebase::write_u32(trap_entry as u32);
-    println!("Set ebase = {:x}", trap_entry as u32);
 
     let mut status = cp0::status::read();
     // Enable IPI

kernel/src/arch/mipsel/mod.rs

@@ -28,7 +28,6 @@ pub extern "C" fn rust_main() -> ! {
     if cpu_id != BOOT_CPU_ID {
         // TODO: run others_main on other CPU
         // while unsafe { !cpu::has_started(hartid) }  { }
-        // println!("Hello RISCV! in hart {}, dtb @ {:#x}", hartid, dtb);
         // others_main();
         loop {}
     }
@@ -45,7 +44,7 @@ pub extern "C" fn rust_main() -> ! {
     timer::init();
     driver::init();
 
-    println!("Hello MIPS 32 from CPU {}, dtb @ {:#x}", cpu_id, dtb_start);
+    info!("Hello MIPS 32 from CPU {}, dtb @ {:#x}", cpu_id, dtb_start);
 
     //crate::drivers::init(dtb_start);
     crate::process::init();

kernel/src/arch/riscv/mod.rs

@@ -42,7 +42,7 @@ pub extern "C" fn rust_main(hartid: usize, device_tree_paddr: usize) -> ! {
         memory::clear_bss();
     }
 
-    println!(
+    info!(
         "Hello RISCV! in hart {}, device tree @ {:#x}",
         hartid, device_tree_vaddr
     );

kernel/src/process/thread.rs

@@ -307,6 +307,11 @@ impl Thread {
             // F | A | D | EL0
             context.spsr = 0b1101_00_0000;
         }
+        #[cfg(target_arch = "mips")]
+        {
+            // UM
+            context.status = 1 << 4;
+        }
 
         let thread = Thread {
             tid: 0, // allocated below