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Fix mipsel serial

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This commit is contained in:
Jiajie Chen 2020-07-09 12:40:50 +08:00
parent 8942bb8eeb
commit 34e53e22b4
3 changed files with 7 additions and 23 deletions
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2
kernel/src/arch/mipsel/board/malta/device.dts
View File

@ -30,8 +30,6 @@
reg = <0xbf000900 0x40>;
reg-shift = <3>;
clock-frequency = <1843200>;
/* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */
interrupt-parent = <&cpu_intc>;
interrupts = <4>;
};

24
kernel/src/arch/mipsel/interrupt/mod.rs
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@ -64,7 +64,7 @@ pub extern "C" fn trap_handler(tf: &mut TrapFrame) {
let cause = cp0::cause::Cause {
bits: tf.cause as u32,
};
debug!("Exception @ CPU{}: {:?} ", 0, cause.cause());
trace!("Exception @ CPU{}: {:?} ", 0, cause.cause());
match cause.cause() {
E::Interrupt => interrupt_dispatcher(tf),
E::Syscall => syscall(tf),
@ -83,30 +83,20 @@ fn interrupt_dispatcher(tf: &mut TrapFrame) {
bits: tf.cause as u32,
};
let pint = cause.pending_interrupt();
// trace!(" Interrupt {:08b} ", pint);
trace!(" Interrupt {:08b} ", pint);
if (pint & 0b100_000_00) != 0 {
timer();
} else if (pint & 0b011_111_00) != 0 {
external();
for i in 0..6 {
if (pint & (1 << i)) != 0 {
IRQ_MANAGER.read().try_handle_interrupt(Some(i));
}
}
} else {
ipi();
}
}
fn external() {
// true means handled, false otherwise
let handlers = [try_process_drivers];
for handler in handlers.iter() {
if handler() == true {
break;
}
}
}
fn try_process_drivers() -> bool {
IRQ_MANAGER.read().try_handle_interrupt(None)
}
fn ipi() {
debug!("IPI");
cp0::cause::reset_soft_int0();

4
kernel/src/shell.rs
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@ -13,10 +13,6 @@ pub fn add_user_shell() {
// This one can transfer env vars!
// Why???
#[cfg(target_arch = "mips")]
let init_shell = "/rust/sh"; //from docker-library
#[cfg(not(target_arch = "mips"))]
let init_shell = "/busybox"; //from docker-library
#[cfg(target_arch = "x86_64")]