mirror of
https://github.com/rcore-os/rCore.git
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Fix aarch64 compilation
This commit is contained in:
Jiajie Chen
parent
aa068944e2
commit
8822964045
12
kernel/src/arch/aarch64/fp.rs
Normal file
12
kernel/src/arch/aarch64/fp.rs
Normal file
@ -0,0 +1,12 @@
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#[derive(Debug, Copy, Clone, Default)]
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pub struct FpState {}
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impl FpState {
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pub fn new() -> Self {
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Self { ..Self::default() }
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}
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pub fn save(&mut self) {}
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pub fn restore(&self) {}
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}
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@ -5,6 +5,7 @@ use core::sync::atomic::{spin_loop_hint, AtomicBool, Ordering};
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mod boot;
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pub mod consts;
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pub mod cpu;
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pub mod fp;
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pub mod interrupt;
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pub mod io;
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pub mod memory;
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@ -1,40 +1,121 @@
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use trapframe::TrapFrame;
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use trapframe::UserContext;
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// mcontext
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#[repr(C)]
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#[derive(Clone, Debug)]
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pub struct MachineContext {
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pub r8: usize,
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pub r9: usize,
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pub r10: usize,
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pub r11: usize,
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pub r12: usize,
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pub r13: usize,
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pub r14: usize,
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pub r15: usize,
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pub rdi: usize,
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pub rsi: usize,
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pub rbp: usize,
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pub rbx: usize,
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pub rdx: usize,
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pub rax: usize,
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pub rcx: usize,
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pub rsp: usize,
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pub rip: usize,
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pub eflags: usize,
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pub cs: u16,
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pub gs: u16,
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pub fs: u16,
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pub _pad: u16,
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pub err: usize,
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pub trapno: usize,
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pub oldmask: usize,
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pub cr2: usize,
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pub fpstate: usize,
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pub _reserved1: [usize; 8],
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fault_address: usize,
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x0: usize,
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x1: usize,
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x2: usize,
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x3: usize,
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x4: usize,
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x5: usize,
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x6: usize,
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x7: usize,
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x8: usize,
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x9: usize,
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x10: usize,
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x11: usize,
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x12: usize,
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x13: usize,
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x14: usize,
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x15: usize,
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x16: usize,
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x17: usize,
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x18: usize,
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x19: usize,
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x20: usize,
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x21: usize,
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x22: usize,
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x23: usize,
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x24: usize,
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x25: usize,
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x26: usize,
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x27: usize,
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x28: usize,
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x29: usize,
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x30: usize,
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sp: usize,
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pc: usize,
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pstate: usize,
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}
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impl MachineContext {
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pub fn from_tf(tf: &TrapFrame) -> Self {
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todo!()
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pub fn from_tf(tf: &UserContext) -> Self {
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Self {
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fault_address: 0,
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x0: tf.general.x0,
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x1: tf.general.x1,
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x2: tf.general.x2,
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x3: tf.general.x3,
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x4: tf.general.x4,
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x5: tf.general.x5,
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x6: tf.general.x6,
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x7: tf.general.x7,
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x8: tf.general.x8,
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x9: tf.general.x9,
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x10: tf.general.x10,
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x11: tf.general.x13,
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x12: tf.general.x12,
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x13: tf.general.x13,
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x14: tf.general.x14,
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x15: tf.general.x15,
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x16: tf.general.x16,
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x17: tf.general.x17,
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x18: tf.general.x18,
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x19: tf.general.x19,
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x20: tf.general.x20,
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x21: tf.general.x21,
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x22: tf.general.x22,
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x23: tf.general.x23,
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x24: tf.general.x24,
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x25: tf.general.x25,
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x26: tf.general.x26,
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x27: tf.general.x27,
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x28: tf.general.x28,
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x29: tf.general.x29,
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x30: tf.general.x30,
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sp: tf.sp,
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pc: tf.elr,
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pstate: tf.spsr,
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}
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}
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pub fn fill_tf(&self, tf: &mut UserContext) {
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tf.general.x0 = self.x0;
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tf.general.x1 = self.x1;
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tf.general.x2 = self.x2;
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tf.general.x3 = self.x3;
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tf.general.x4 = self.x4;
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tf.general.x5 = self.x5;
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tf.general.x6 = self.x6;
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tf.general.x7 = self.x7;
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tf.general.x8 = self.x8;
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tf.general.x9 = self.x9;
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tf.general.x10 = self.x10;
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tf.general.x11 = self.x11;
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tf.general.x12 = self.x12;
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tf.general.x13 = self.x13;
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tf.general.x14 = self.x14;
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tf.general.x15 = self.x15;
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tf.general.x16 = self.x16;
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tf.general.x17 = self.x17;
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tf.general.x18 = self.x18;
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tf.general.x19 = self.x19;
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tf.general.x20 = self.x20;
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tf.general.x21 = self.x21;
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tf.general.x22 = self.x22;
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tf.general.x23 = self.x23;
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tf.general.x24 = self.x24;
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tf.general.x25 = self.x25;
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tf.general.x26 = self.x26;
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tf.general.x27 = self.x27;
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tf.general.x28 = self.x28;
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tf.general.x29 = self.x29;
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tf.general.x30 = self.x30;
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tf.sp = self.sp;
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tf.elr = self.pc;
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tf.spsr = self.pstate;
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}
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}
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@ -15,25 +15,25 @@ use core::time::Duration;
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pub const BLOCK_SIZE: usize = 512;
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const SD_CMD_TYPE_NORMAL: u32 = 0x0;
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const SD_CMD_TYPE_SUSPEND: u32 = (1 << 22);
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const SD_CMD_TYPE_RESUME: u32 = (2 << 22);
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const SD_CMD_TYPE_ABORT: u32 = (3 << 22);
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const SD_CMD_TYPE_MASK: u32 = (3 << 22);
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const SD_CMD_ISDATA: u32 = (1 << 21);
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const SD_CMD_IXCHK_EN: u32 = (1 << 20);
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const SD_CMD_CRCCHK_EN: u32 = (1 << 19);
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const SD_CMD_TYPE_SUSPEND: u32 = 1 << 22;
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const SD_CMD_TYPE_RESUME: u32 = 2 << 22;
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const SD_CMD_TYPE_ABORT: u32 = 3 << 22;
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const SD_CMD_TYPE_MASK: u32 = 3 << 22;
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const SD_CMD_ISDATA: u32 = 1 << 21;
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const SD_CMD_IXCHK_EN: u32 = 1 << 20;
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const SD_CMD_CRCCHK_EN: u32 = 1 << 19;
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const SD_CMD_RSPNS_TYPE_NONE: u32 = 0; // For no response
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const SD_CMD_RSPNS_TYPE_136: u32 = (1 << 16); // For response R2 (with CRC), R3,4 (no CRC)
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const SD_CMD_RSPNS_TYPE_48: u32 = (2 << 16); // For responses R1, R5, R6, R7 (with CRC)
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const SD_CMD_RSPNS_TYPE_48B: u32 = (3 << 16); // For responses R1b, R5b (with CRC)
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const SD_CMD_RSPNS_TYPE_MASK: u32 = (3 << 16);
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const SD_CMD_MULTI_BLOCK: u32 = (1 << 5);
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const SD_CMD_RSPNS_TYPE_136: u32 = 1 << 16; // For response R2 (with CRC), R3,4 (no CRC)
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const SD_CMD_RSPNS_TYPE_48: u32 = 2 << 16; // For responses R1, R5, R6, R7 (with CRC)
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const SD_CMD_RSPNS_TYPE_48B: u32 = 3 << 16; // For responses R1b, R5b (with CRC)
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const SD_CMD_RSPNS_TYPE_MASK: u32 = 3 << 16;
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const SD_CMD_MULTI_BLOCK: u32 = 1 << 5;
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const SD_CMD_DAT_DIR_HC: u32 = 0;
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const SD_CMD_DAT_DIR_CH: u32 = (1 << 4);
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const SD_CMD_DAT_DIR_CH: u32 = 1 << 4;
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const SD_CMD_AUTO_CMD_EN_NONE: u32 = 0;
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const SD_CMD_AUTO_CMD_EN_CMD12: u32 = (1 << 2);
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const SD_CMD_AUTO_CMD_EN_CMD23: u32 = (2 << 2);
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const SD_CMD_BLKCNT_EN: u32 = (1 << 1);
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const SD_CMD_AUTO_CMD_EN_CMD12: u32 = 1 << 2;
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const SD_CMD_AUTO_CMD_EN_CMD23: u32 = 2 << 2;
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const SD_CMD_BLKCNT_EN: u32 = 1 << 1;
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const SD_CMD_DMA: u32 = 1;
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const SD_ERR_BASE: u32 = 16;
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@ -50,13 +50,13 @@ const SD_ERR_ADMA: u32 = 9; // !(not supported)
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const SD_ERR_TUNING: u32 = 10; // !(not supported)
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const SD_ERR_RSVD: u32 = 11; // !(not supported)
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const SD_ERR_MASK_CMD_TIMEOUT: u32 = (1 << (16 + SD_ERR_CMD_TIMEOUT));
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const SD_ERR_MASK_CMD_CRC: u32 = (1 << (16 + SD_ERR_CMD_CRC));
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const SD_ERR_MASK_CMD_END_BIT: u32 = (1 << (16 + SD_ERR_CMD_END_BIT));
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const SD_ERR_MASK_CMD_INDEX: u32 = (1 << (16 + SD_ERR_CMD_INDEX));
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const SD_ERR_MASK_DATA_TIMEOUT: u32 = (1 << (16 + SD_ERR_CMD_TIMEOUT));
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const SD_ERR_MASK_DATA_CRC: u32 = (1 << (16 + SD_ERR_CMD_CRC));
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const SD_ERR_MASK_DATA_END_BIT: u32 = (1 << (16 + SD_ERR_CMD_END_BIT));
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const SD_ERR_MASK_CMD_TIMEOUT: u32 = 1 << (16 + SD_ERR_CMD_TIMEOUT);
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const SD_ERR_MASK_CMD_CRC: u32 = 1 << (16 + SD_ERR_CMD_CRC);
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const SD_ERR_MASK_CMD_END_BIT: u32 = 1 << (16 + SD_ERR_CMD_END_BIT);
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const SD_ERR_MASK_CMD_INDEX: u32 = 1 << (16 + SD_ERR_CMD_INDEX);
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const SD_ERR_MASK_DATA_TIMEOUT: u32 = 1 << (16 + SD_ERR_CMD_TIMEOUT);
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const SD_ERR_MASK_DATA_CRC: u32 = 1 << (16 + SD_ERR_CMD_CRC);
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const SD_ERR_MASK_DATA_END_BIT: u32 = 1 << (16 + SD_ERR_CMD_END_BIT);
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// const SD_ERR_MASK_CURRENT_LIMIT: u32 = (1 << (16 + SD_ERR_CMD_CURRENT_LIMIT));
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// const SD_ERR_MASK_AUTO_CMD12: u32 = (1 << (16 + SD_ERR_CMD_AUTO_CMD12));
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// const SD_ERR_MASK_ADMA: u32 = (1 << (16 + SD_ERR_CMD_ADMA));
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@ -73,18 +73,18 @@ const SD_CARD_REMOVAL: u32 = 1 << 7;
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const SD_CARD_INTERRUPT: u32 = 1 << 8;
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const SD_RESP_NONE: u32 = SD_CMD_RSPNS_TYPE_NONE;
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const SD_RESP_R1: u32 = (SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN);
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const SD_RESP_R1b: u32 = (SD_CMD_RSPNS_TYPE_48B | SD_CMD_CRCCHK_EN);
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const SD_RESP_R2: u32 = (SD_CMD_RSPNS_TYPE_136 | SD_CMD_CRCCHK_EN);
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const SD_RESP_R1: u32 = SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN;
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const SD_RESP_R1b: u32 = SD_CMD_RSPNS_TYPE_48B | SD_CMD_CRCCHK_EN;
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const SD_RESP_R2: u32 = SD_CMD_RSPNS_TYPE_136 | SD_CMD_CRCCHK_EN;
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const SD_RESP_R3: u32 = SD_CMD_RSPNS_TYPE_48;
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const SD_RESP_R4: u32 = SD_CMD_RSPNS_TYPE_136;
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const SD_RESP_R5: u32 = (SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN);
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const SD_RESP_R5b: u32 = (SD_CMD_RSPNS_TYPE_48B | SD_CMD_CRCCHK_EN);
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const SD_RESP_R6: u32 = (SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN);
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const SD_RESP_R7: u32 = (SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN);
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const SD_RESP_R5: u32 = SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN;
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const SD_RESP_R5b: u32 = SD_CMD_RSPNS_TYPE_48B | SD_CMD_CRCCHK_EN;
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const SD_RESP_R6: u32 = SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN;
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const SD_RESP_R7: u32 = SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN;
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const SD_DATA_READ: u32 = (SD_CMD_ISDATA | SD_CMD_DAT_DIR_CH);
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const SD_DATA_WRITE: u32 = (SD_CMD_ISDATA | SD_CMD_DAT_DIR_HC);
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const SD_DATA_READ: u32 = SD_CMD_ISDATA | SD_CMD_DAT_DIR_CH;
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const SD_DATA_WRITE: u32 = SD_CMD_ISDATA | SD_CMD_DAT_DIR_HC;
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const SD_VER_UNKNOWN: u32 = 0;
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const SD_VER_1: u32 = 1;
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@ -277,17 +277,17 @@ macro_rules! ACMD {
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(($a) | (IS_APP_CMD))
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};
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}
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const SET_BUS_WIDTH: u32 = (6 | IS_APP_CMD);
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const SD_STATUS: u32 = (13 | IS_APP_CMD);
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const SEND_NUM_WR_BLOCKS: u32 = (22 | IS_APP_CMD);
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const SET_WR_BLK_ERASE_COUNT: u32 = (23 | IS_APP_CMD);
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const SD_SEND_OP_COND: u32 = (41 | IS_APP_CMD);
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const SET_CLR_CARD_DETECT: u32 = (42 | IS_APP_CMD);
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const SEND_SCR: u32 = (51 | IS_APP_CMD);
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const SET_BUS_WIDTH: u32 = 6 | IS_APP_CMD;
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const SD_STATUS: u32 = 13 | IS_APP_CMD;
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const SEND_NUM_WR_BLOCKS: u32 = 22 | IS_APP_CMD;
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const SET_WR_BLK_ERASE_COUNT: u32 = 23 | IS_APP_CMD;
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const SD_SEND_OP_COND: u32 = 41 | IS_APP_CMD;
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const SET_CLR_CARD_DETECT: u32 = 42 | IS_APP_CMD;
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const SEND_SCR: u32 = 51 | IS_APP_CMD;
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const SD_RESET_CMD: u32 = (1 << 25);
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const SD_RESET_DAT: u32 = (1 << 26);
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const SD_RESET_ALL: u32 = (1 << 24);
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const SD_RESET_CMD: u32 = 1 << 25;
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const SD_RESET_DAT: u32 = 1 << 26;
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const SD_RESET_ALL: u32 = 1 << 24;
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#[repr(C)]
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#[derive(Debug)]
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@ -483,15 +483,10 @@ impl EmmcCtl {
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}
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pub fn sd_get_clock_divider(&mut self, base_clock: u32, target_rate: u32) -> u32 {
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let targetted_divisor: u32 = if (target_rate > base_clock) {
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let targetted_divisor: u32 = if target_rate > base_clock {
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1
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} else {
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base_clock / target_rate
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- if (base_clock % target_rate != 0) {
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1
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} else {
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0
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}
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base_clock / target_rate - if base_clock % target_rate != 0 { 1 } else { 0 }
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};
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let mut divisor = 31;
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@ -548,7 +543,7 @@ impl EmmcCtl {
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usleep(2000);
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// Enable the SD clock
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control1 |= (1 << 2);
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control1 |= 1 << 2;
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self.emmc.registers.CONTROL1.write(control1);
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usleep(2000);
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@ -776,7 +771,7 @@ impl EmmcCtl {
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);
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if self.sd_issue_command_int_pre(command, 0, timeout) {
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let mut buf = &mut self.sd_scr.scr;
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let mut wr_irpt = (1 << 5);
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let mut wr_irpt = 1 << 5;
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let mut finished = true;
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for cur_block in 0..count {
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timeout_wait!(
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@ -793,7 +788,7 @@ impl EmmcCtl {
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break;
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}
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let mut cur_word_no = 0;
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while (cur_word_no < blocks_size_u32) {
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while cur_word_no < blocks_size_u32 {
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let word = self.emmc.registers.DATA.read();
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debug!(
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"EmmcCtl: block#{}, word#{} = 0x{:08X}, pos = {}",
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@ -886,7 +881,7 @@ impl EmmcCtl {
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let mut control0 = self.emmc.registers.CONTROL0.read();
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let mut control1 = self.emmc.registers.CONTROL1.read();
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control1 |= (1 << 24);
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control1 |= 1 << 24;
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// Disable clock
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control1 &= !(1 << 2);
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control1 &= !(1 << 0);
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@ -919,7 +914,7 @@ impl EmmcCtl {
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let f_id = self.sd_get_clock_divider(base_clock, 400000);
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control1 |= f_id;
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control1 |= (7 << 16); // data timeout = TMCLK * 2^10
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control1 |= 7 << 16; // data timeout = TMCLK * 2^10
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self.emmc.registers.CONTROL1.write(control1);
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@ -1006,9 +1001,9 @@ impl EmmcCtl {
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while card_is_busy {
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let v2_flags = if v2_later {
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(1 << 30)
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1 << 30
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| if self.failed_voltage_switch == 0 {
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(1 << 24)
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1 << 24
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} else {
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0
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}
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@ -1043,7 +1038,7 @@ impl EmmcCtl {
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// Switch to 1.8V mode if possible
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debug!("EmmcCtl: card_supports_18v = {}", self.card_supports_18v);
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if (self.card_supports_18v) {
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if self.card_supports_18v {
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// As per HCSS 3.6.1
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debug!("EmmcCtl: Switch to 1.8v mode.");
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||||
// Send VOLTAGE_SWITCH
|
||||
@ -1068,7 +1063,7 @@ impl EmmcCtl {
|
||||
|
||||
// Set 1.8V signal enable to 1
|
||||
control0 = self.emmc.registers.CONTROL0.read();
|
||||
control0 |= (1 << 8);
|
||||
control0 |= 1 << 8;
|
||||
self.emmc.registers.CONTROL0.write(control0);
|
||||
|
||||
usleep(5000);
|
||||
@ -1083,7 +1078,7 @@ impl EmmcCtl {
|
||||
|
||||
// Re-enable SD clock
|
||||
control1 = self.emmc.registers.CONTROL1.read();
|
||||
control1 |= (1 << 2);
|
||||
control1 |= 1 << 2;
|
||||
self.emmc.registers.CONTROL1.write(control1);
|
||||
|
||||
// Wait 1 ms
|
||||
@ -1170,7 +1165,7 @@ impl EmmcCtl {
|
||||
|
||||
self.block_size = 512;
|
||||
let mut controller_block_size = self.emmc.registers.BLKSIZECNT.read();
|
||||
controller_block_size &= (!0xfff);
|
||||
controller_block_size &= !0xfff;
|
||||
controller_block_size |= 0x200;
|
||||
self.emmc.registers.BLKSIZECNT.write(controller_block_size);
|
||||
|
||||
@ -1292,7 +1287,7 @@ impl EmmcCtl {
|
||||
// send command
|
||||
self.last_cmd = command;
|
||||
if self.sd_issue_command_int_pre(sd_commands[command as usize], block_no, 500000) {
|
||||
let mut wr_irpt = (1 << 5);
|
||||
let mut wr_irpt = 1 << 5;
|
||||
let mut finished = true;
|
||||
for cur_block in 0..count {
|
||||
timeout_wait!(
|
||||
@ -1308,7 +1303,7 @@ impl EmmcCtl {
|
||||
break;
|
||||
}
|
||||
let mut cur_word_no = 0;
|
||||
while (cur_word_no < blocks_size_u32) {
|
||||
while cur_word_no < blocks_size_u32 {
|
||||
buf[(cur_block as usize) * blocks_size_u32 + cur_word_no] =
|
||||
self.emmc.registers.DATA.read();
|
||||
cur_word_no += 1;
|
||||
@ -1350,7 +1345,7 @@ impl EmmcCtl {
|
||||
// send command
|
||||
self.last_cmd = command;
|
||||
if self.sd_issue_command_int_pre(sd_commands[command as usize], block_no, 500000) {
|
||||
let mut wr_irpt = (1 << 4);
|
||||
let mut wr_irpt = 1 << 4;
|
||||
let mut finished = true;
|
||||
for cur_block in 0..count {
|
||||
timeout_wait!(
|
||||
@ -1366,7 +1361,7 @@ impl EmmcCtl {
|
||||
break;
|
||||
}
|
||||
let mut cur_word_no = 0;
|
||||
while (cur_word_no < blocks_size_u32) {
|
||||
while cur_word_no < blocks_size_u32 {
|
||||
self.emmc
|
||||
.registers
|
||||
.DATA
|
||||
|
||||
@ -13,11 +13,14 @@
|
||||
#![deny(stable_features)]
|
||||
#![deny(unused_unsafe)]
|
||||
#![deny(ellipsis_inclusive_range_patterns)]
|
||||
#![deny(unused_parens)]
|
||||
#![allow(non_upper_case_globals)]
|
||||
#![allow(dead_code)]
|
||||
#![allow(unused_mut)]
|
||||
#![allow(unused_variables)]
|
||||
#![allow(unused_imports)]
|
||||
#![allow(unreachable_patterns)]
|
||||
#![allow(unused_assignments)]
|
||||
#![no_std]
|
||||
|
||||
// just keep it ...
|
||||
|
||||
@ -335,7 +335,6 @@ impl Syscall<'_> {
|
||||
)
|
||||
.await
|
||||
}
|
||||
#[cfg(target_arch = "x86_64")]
|
||||
SYS_TKILL => self.sys_tkill(args[0], args[1]),
|
||||
|
||||
// time
|
||||
|
||||
Loading…
Reference in New Issue
Block a user