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Author	SHA1	Message	Date
Jiajie Chen	7b9c85840e	Implement IPC_SET for sem	2020-06-30 14:08:25 +08:00
Jiajie Chen	6a0e25431b	Some code cleanup	2020-06-30 13:05:38 +08:00
Jiajie Chen	21f024c76d	Remove non snake case names	2020-06-30 12:59:17 +08:00
Jiajie Chen	427a338095	Merge branch 'master' into pull-30-merge	2020-06-30 12:55:05 +08:00
Chen	723f3d7803	Merge pull request #61 from rcore-os/refactor ... Refactor	2020-06-30 12:43:58 +08:00
Jiajie Chen	16eb1ed7e2	Move arch specific code to arch	2020-06-30 12:27:29 +08:00
Jiajie Chen	8822964045	Fix aarch64 compilation	2020-06-30 09:47:51 +08:00
Jiajie Chen	aa068944e2	Add rtc goldfish and dummy fp for riscv	2020-06-30 09:12:17 +08:00
Jiajie Chen	8823ba9034	Fix typo in last commit	2020-06-29 23:22:45 +08:00
Jiajie Chen	71015ef63c	Setup x87 FPU control word correctly	2020-06-29 23:21:11 +08:00
Jiajie Chen	e32597ac82	Add fp save and restore and use accel=hvf in macOS	2020-06-29 22:53:30 +08:00
Jiajie Chen	34ca9963cb	Fix signal masking	2020-06-29 20:48:42 +08:00
Jiajie Chen	8f0b2702f0	Get mcontext back for pthread_cancel	2020-06-29 12:03:29 +08:00
Jiajie Chen	7ba001a0fa	Document and cleanup signal code	2020-06-29 11:49:03 +08:00
Jiajie Chen	68609a0f7c	Add yield to avoid starvation	2020-06-29 11:09:21 +08:00
Jiajie Chen	bc525e1902	Cleanup signal code	2020-06-28 23:21:22 +08:00
Jiajie Chen	25382e211e	Support signal in sleep	2020-06-28 22:21:52 +08:00
Jiajie Chen	5165269f4b	Cleanup signal code and move sig alt stack to thread	2020-06-28 21:35:40 +08:00
Jiajie Chen	d33448b91e	Ease riscv32/64 check, fix riscv32	2020-06-26 23:39:27 +08:00
Jiajie Chen	611aaa5f01	Update dependencies	2020-06-26 23:23:57 +08:00
Jiajie Chen	00ac4c2dfa	Remove thinpad, until we are able to test on it again	2020-06-26 22:31:40 +08:00
Jiajie Chen	2dca1399be	Remove k210, until we are able to test on it again again	2020-06-26 22:30:01 +08:00
Jiajie Chen	1f9d7cd323	Use prebuilt image correctly	2020-06-26 22:11:56 +08:00
Jiajie Chen	e21a76cb50	Bump versions	2020-06-26 21:56:12 +08:00
Runji Wang	9d82b29517	move wait_for_interrupt from executor to kernel	2020-06-24 00:09:52 +08:00
Jiajie Chen	7479293a11	Cleanup code	2020-06-23 20:59:04 +08:00
Jiajie Chen	0290937833	Code cleanup	2020-06-23 20:46:36 +08:00
Jiajie Chen	d895f43d9a	Fix bcm2837 serial	2020-06-23 19:59:36 +08:00
Jiajie Chen	55de8e6dcf	Move raspi drivers out of arch, fix aarch64 trap handling and add spec.md	2020-06-22 22:51:32 +08:00
Jiajie Chen	a56e2b54e0	Fix is_page_fault in aarch64	2020-06-22 18:48:43 +08:00
Jiajie Chen	62de55de9d	Use wrappers from riscv	2020-06-22 11:52:12 +08:00
Jiajie Chen	3aaaa28c41	Remove k210, until we are able to test on it again	2020-06-22 11:44:43 +08:00
Jiajie Chen	433c28bc5b	Minor update	2020-06-22 11:41:27 +08:00
Jiajie Chen	d08c14152b	Fix aarch64	2020-06-21 23:36:48 +08:00
equation314	e218399113	aarch64: add bcm2835 sdhci as block driver ... Now can load user programs from the SD card, but too slow to read/write	2020-06-21 18:55:29 +08:00
Jiajie Chen	458347c1c0	Fix aarch64 compilation	2020-06-21 15:54:15 +08:00
Jiajie Chen	fd59658355	Unify trap_handler interfaces	2020-06-21 11:38:31 +08:00
Jiajie Chen	1560e1c3f8	Fix riscv smp, maybe	2020-06-21 11:16:44 +08:00
Jiajie Chen	93f376ee8d	Move sigset, add missing sfence_vma_all	2020-06-21 10:58:37 +08:00
Jiajie Chen	0086768392	Use tp to save hart id in riscv	2020-06-21 10:43:53 +08:00
Jiajie Chen	698732105b	Set interrupt bits in plic	2020-06-21 08:59:15 +08:00
Jiajie Chen	61def0f1c9	Register uart16550 interrupt to plic	2020-06-21 08:53:09 +08:00
Jiajie Chen	5006ef952f	Initial irq manager and add device tree registry	2020-06-21 08:04:49 +08:00
Jiajie Chen	d7def80d82	Remove unused rocket chip code	2020-06-20 23:04:37 +08:00
Jiajie Chen	3fd2d0b349	Remove unused router code and cleanup	2020-06-20 22:58:13 +08:00
Jiajie Chen	8ead1f85e8	Fix riscv fork	2020-06-20 22:47:20 +08:00
Jiajie Chen	f74eaeb11f	Remove sbi console	2020-06-20 22:29:15 +08:00
Jiajie Chen	3ac4d7a607	Fix riscv external interrupt	2020-06-20 22:25:34 +08:00
Jiajie Chen	b3f86cc3d1	Use uart16550 as serial in riscv as well	2020-06-20 22:06:45 +08:00
Jiajie Chen	548495a149	Enable signal in riscv	2020-06-20 17:40:51 +08:00