Use wrappers from riscv

kernel/src/arch/riscv/board/k210/linker.ld

@@ -1,52 +0,0 @@
-/* Copy from bbl-ucore : https://ring00.github.io/bbl-ucore      */
-
-/* Simple linker script for the ucore kernel.
-   See the GNU ld 'info' manual ("info ld") to learn the syntax. */
-
-OUTPUT_ARCH(riscv)
-ENTRY(_start)
-
-BASE_ADDRESS = 0xffffffffc0010000;
-
-SECTIONS
-{
-    /* Load the kernel at this address: "." means the current address */
-    . = BASE_ADDRESS;
-    start = .;
-
-    .text : {
-        stext = .;
-        *(.text.entry)
-        _copy_user_start = .;
-        *(.text.copy_user)
-        _copy_user_end = .;
-        *(.text .text.*)
-        . = ALIGN(4K);
-        etext = .;
-    }
-
-    .rodata : {
-        srodata = .;
-        *(.rodata .rodata.*)
-        . = ALIGN(4K);
-        erodata = .;
-    }
-
-    .data : {
-        sdata = .;
-        *(.data .data.*)
-        edata = .;
-    }
-
-    .stack : {
-        *(.bss.stack)
-    }
-
-    .bss : {
-        sbss = .;
-        *(.bss .bss.*)
-        ebss = .;
-    }
-
-    PROVIDE(end = .);
-}

kernel/src/arch/riscv/boot/entry_k210.asm

@@ -1,30 +0,0 @@
-    .section .text.entry
-    .globl _start
-_start:
-    # a0 == hartid
-    # pc == 0x80010000
-    # sp == 0x8000xxxx
-
-    # 1. set sp
-    # sp = bootstack + (hartid + 1) * 0x10000
-    add     t0, a0, 1
-    slli    t0, t0, 14
-    lui     sp, %hi(bootstack)
-    add     sp, sp, t0
-
-    # 1.1 set device tree paddr
-    # OpenSBI give me 0 ???
-    li      a1, 0x800003b0
-
-    # 2. jump to rust_main (absolute address)
-    lui     t0, %hi(rust_main)
-    addi    t0, t0, %lo(rust_main)
-    jr      t0
-
-    .section .bss.stack
-    .align 12   # page align
-    .global bootstack
-bootstack:
-    .space 4096 * 4 * 2
-    .global bootstacktop
-bootstacktop:

kernel/src/arch/riscv/io.rs

@@ -7,5 +7,5 @@ pub fn putfmt(fmt: Arguments) {
     if let Some(serial) = drivers.first_mut() {
         serial.write(format!("{}", fmt).as_bytes());
     }
-    // might miss some early messages
+    // might miss some early messages, but it's okay
 }

kernel/src/arch/riscv/memory.rs

@@ -21,7 +21,8 @@ pub fn init(dtb: usize) {
 pub fn init_other() {
     unsafe {
         sstatus::set_sum(); // Allow user memory access
-        llvm_asm!("csrw satp, $0; sfence.vma" :: "r"(SATP) :: "volatile");
+        satp::write(SATP);
+        sfence_vma_all();
     }
 }
 

kernel/src/arch/riscv/paging.rs

@@ -7,6 +7,7 @@ use riscv::addr::*;
 use riscv::asm::{sfence_vma, sfence_vma_all};
 use riscv::paging::{FrameAllocator, FrameDeallocator};
 use riscv::paging::{Mapper, PageTable as RvPageTable, PageTableEntry, PageTableFlags as EF};
+use riscv::register::satp;
 
 #[cfg(target_arch = "riscv32")]
 type TopLevelPageTable<'a> = riscv::paging::Rv32PageTable<'a>;
@@ -216,15 +217,11 @@ impl PageTableExt for PageTableImpl {
     }
 
     unsafe fn set_token(token: usize) {
-        llvm_asm!("csrw satp, $0" :: "r"(token) :: "volatile");
+        satp::write(token);
     }
 
     fn active_token() -> usize {
-        let mut token;
-        unsafe {
-            llvm_asm!("csrr $0, satp" : "=r"(token) ::: "volatile");
-        }
-        token
+        satp::read().bits()
     }
 
     fn flush_tlb() {

kernel/src/arch/riscv/timer.rs

@@ -3,12 +3,12 @@ use core::time::Duration;
 use log::*;
 use riscv::register::*;
 
-#[cfg(target_pointer_width = "64")]
+#[cfg(target_arch = "riscv64")]
 pub fn get_cycle() -> u64 {
     time::read() as u64
 }
 
-#[cfg(target_pointer_width = "32")]
+#[cfg(target_arch = "riscv32")]
 pub fn get_cycle() -> u64 {
     loop {
         let hi = timeh::read();