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Remove unused rocket chip code

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This commit is contained in:
Jiajie Chen 2020-06-20 23:04:37 +08:00
parent 3fd2d0b349
commit d7def80d82
9 changed files with 3 additions and 430 deletions
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119
kernel/src/arch/riscv/board/rocket_chip/device.dts
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@ -1,119 +0,0 @@
/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "freechips,rocketchip-unknown-dev";
model = "freechips,rocketchip-unknown";
L14: cpus {
#address-cells = <1>;
#size-cells = <0>;
L5: cpu@0 {
clock-frequency = <0>;
compatible = "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <16384>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <16384>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&L6>;
reg = <0>;
riscv,isa = "rv64imafdc";
status = "okay";
timebase-frequency = <1000000>;
tlb-split;
L3: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
L6: memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
L13: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "freechips,rocketchip-unknown-soc", "simple-bus";
ranges;
L11: blkdev-controller@10015000 {
compatible = "ucbbar,blkdev";
interrupt-parent = <&L0>;
interrupts = <3>;
reg = <0x10015000 0x1000>;
reg-names = "control";
};
L1: clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&L3 3 &L3 7>;
reg = <0x2000000 0x10000>;
reg-names = "control";
};
L2: debug-controller@0 {
compatible = "sifive,debug-013", "riscv,debug-013";
interrupts-extended = <&L3 65535>;
reg = <0x0 0x1000>;
reg-names = "control";
};
L8: error-device@3000 {
compatible = "sifive,error0";
reg = <0x3000 0x1000>;
reg-names = "mem";
};
L10: external-interrupts {
interrupt-parent = <&L0>;
interrupts = <1 2>;
};
L0: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <&L3 11 &L3 9>;
reg = <0xc000000 0x4000000>;
reg-names = "control";
riscv,max-priority = <7>;
riscv,ndev = <3>;
};
L7: mmio-port-axi4@60000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x60000000 0x60000000 0x20000000>;
serial0: serial@60000000 {
compatible = "xlnx,xps-uartlite-1.00.a";
reg = <0x6000000 0x1000>;
interrupt-parent = <&axi_intc>;
interrupts = <1>;
};
axi_intc: axi_intc@61200000 {
compatible = "xlnx,xps-intc-1.00.a";
reg = <0x61200000 0x1000>;
interrupt-parent = <&L10>;
interrupts = <0>;
};
router: router@64A00000 {
compatible = "rcore,router";
reg = <0x64A00000 0x1000>;
interrupt-parent = <&L10>;
interrupts = <1>;
};
};
L9: rom@10000 {
compatible = "sifive,rom0";
reg = <0x10000 0x10000>;
reg-names = "mem";
};
};
};

53
kernel/src/arch/riscv/board/rocket_chip/linker.ld
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@ -1,53 +0,0 @@
/* Copy from bbl-ucore : https://ring00.github.io/bbl-ucore */
/* Simple linker script for the ucore kernel.
See the GNU ld 'info' manual ("info ld") to learn the syntax. */
OUTPUT_ARCH(riscv)
ENTRY(_start)
BASE_ADDRESS = 0xffffffffc0200000;
SECTIONS
{
/* Load the kernel at this address: "." means the current address */
. = BASE_ADDRESS;
start = .;
.text : {
stext = .;
*(.text.entry)
_copy_user_start = .;
*(.text.copy_user)
_copy_user_end = .;
*(.text .text.*)
. = ALIGN(4K);
etext = .;
}
.rodata : {
srodata = .;
*(.rodata .rodata.*)
*(.dtb)
. = ALIGN(4K);
erodata = .;
}
.data : {
sdata = .;
*(.data .data.*)
edata = .;
}
.stack : {
*(.bss.stack)
}
.bss : {
sbss = .;
*(.bss .bss.*)
ebss = .;
}
PROVIDE(end = .);
}

48
kernel/src/arch/riscv/board/rocket_chip/mod.rs
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@ -1,48 +0,0 @@
use crate::memory::phys_to_virt;
/// Device tree bytes
pub static DTB: &'static [u8] = include_bytes!("device.dtb");
/// Mask all external interrupt except serial.
pub unsafe fn init_external_interrupt() {
const HART0_S_MODE_INTERRUPT_ENABLES: *mut u64 = phys_to_virt(0x0C00_2080) as *mut u64;
// enable all external interrupts
HART0_S_MODE_INTERRUPT_ENABLES.write_volatile(0xf);
// mask interrupts first
const AXI_INTC_IER: *mut u32 = phys_to_virt(0x6120_0008) as *mut u32;
AXI_INTC_IER.write_volatile(0x0);
// acknowledge all interrupts
const AXI_INTC_IAR: *mut u32 = phys_to_virt(0x6120_000C) as *mut u32;
AXI_INTC_IAR.write_volatile(0xffffffff);
const AXI_INTC_MER: *mut u32 = phys_to_virt(0x6120_001C) as *mut u32;
// Hardware Interrupt enable | Enable irq output
AXI_INTC_MER.write_volatile(0b11);
// enable all interrupts
AXI_INTC_IER.write_volatile(0xffffffff);
}
/// Claim and complete external interrupt by reading and writing to
/// PLIC Interrupt Claim/Complete Register.
pub unsafe fn handle_external_interrupt() {
const HART0_S_MODE_INTERRUPT_CLAIM_COMPLETE: *mut u32 = phys_to_virt(0x0C20_1004) as *mut u32;
// claim
let source = HART0_S_MODE_INTERRUPT_CLAIM_COMPLETE.read_volatile();
// complete
HART0_S_MODE_INTERRUPT_CLAIM_COMPLETE.write_volatile(source);
// acknowledge all interrupts
const AXI_INTC_IAR: *mut u32 = phys_to_virt(0x6120_000C) as *mut u32;
AXI_INTC_IAR.write_volatile(0xffffffff);
}
pub unsafe fn enable_serial_interrupt() {
const SERIAL_BASE: *mut u32 = phys_to_virt(0x60000000) as *mut u32;
const UART_CTRL_REG: usize = 3;
// Intr enable | rx reset | tx reset
const UART_IE: u32 = 0x13;
SERIAL_BASE.add(UART_CTRL_REG).write_volatile(UART_IE);
}

129
kernel/src/arch/riscv/boot/trap.asm
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@ -1,129 +0,0 @@
# Constants / Macros defined in Rust code:
# XLENB
# LOAD
# STORE
.macro SAVE_ALL
# If coming from userspace, preserve the user stack pointer and load
# the kernel stack pointer. If we came from the kernel, sscratch
# will contain 0, and we should continue on the current stack.
csrrw sp, sscratch, sp
bnez sp, trap_from_user
trap_from_kernel:
csrr sp, sscratch
STORE gp, -36
# sscratch = previous-sp, sp = kernel-sp
trap_from_user:
# provide room for trap frame
addi sp, sp, -36 * XLENB
# save x registers except x2 (sp)
STORE x1, 1
STORE x3, 3
STORE x4, 4
STORE x5, 5
STORE x6, 6
STORE x7, 7
STORE x8, 8
STORE x9, 9
STORE x10, 10
STORE x11, 11
STORE x12, 12
STORE x13, 13
STORE x14, 14
STORE x15, 15
STORE x16, 16
STORE x17, 17
STORE x18, 18
STORE x19, 19
STORE x20, 20
STORE x21, 21
STORE x22, 22
STORE x23, 23
STORE x24, 24
STORE x25, 25
STORE x26, 26
STORE x27, 27
STORE x28, 28
STORE x29, 29
STORE x30, 30
STORE x31, 31
# load hartid to gp from sp[0]
LOAD gp, 0
# get sp, sstatus, sepc, stval, scause
# set sscratch = 0
csrrw s0, sscratch, x0
csrr s1, sstatus
csrr s2, sepc
csrr s3, stval
csrr s4, scause
# store sp, sstatus, sepc, sbadvaddr, scause
STORE s0, 2
STORE s1, 32
STORE s2, 33
STORE s3, 34
STORE s4, 35
.endm
.macro RESTORE_ALL
LOAD s1, 32 # s1 = sstatus
LOAD s2, 33 # s2 = sepc
andi s0, s1, 1 << 8 # sstatus.SPP = 1
bnez s0, _to_kernel # s0 = back to kernel?
_to_user:
addi s0, sp, 36*XLENB
csrw sscratch, s0 # sscratch = kernel-sp
STORE gp, 0 # store hartid from gp to sp[0]
_to_kernel:
# restore sstatus, sepc
csrw sstatus, s1
csrw sepc, s2
# restore x registers except x2 (sp)
LOAD x1, 1
LOAD x3, 3
LOAD x4, 4
LOAD x5, 5
LOAD x6, 6
LOAD x7, 7
LOAD x8, 8
LOAD x9, 9
LOAD x10, 10
LOAD x11, 11
LOAD x12, 12
LOAD x13, 13
LOAD x14, 14
LOAD x15, 15
LOAD x16, 16
LOAD x17, 17
LOAD x18, 18
LOAD x19, 19
LOAD x20, 20
LOAD x21, 21
LOAD x22, 22
LOAD x23, 23
LOAD x24, 24
LOAD x25, 25
LOAD x26, 26
LOAD x27, 27
LOAD x28, 28
LOAD x29, 29
LOAD x30, 30
LOAD x31, 31
# restore sp last
LOAD x2, 2
.endm
.section .text
.align 4
.globl trap_entry
trap_entry:
SAVE_ALL
mv a0, sp
jal rust_trap
.globl trap_return
trap_return:
RESTORE_ALL
# return from supervisor call
sret

2
kernel/src/arch/riscv/interrupt/mod.rs
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@ -48,7 +48,7 @@ pub extern "C" fn trap_handler(scause: Scause, stval: usize, tf: &mut TrapFrame)
}
fn external() {
#[cfg(any(feature = "board_u540", feature = "board_rocket_chip"))]
#[cfg(feature = "board_u540")]
unsafe {
super::board::handle_external_interrupt();
}

35
kernel/src/arch/riscv/mod.rs
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@ -3,10 +3,7 @@ use trapframe;
#[cfg(feature = "board_u540")]
#[path = "board/u540/mod.rs"]
pub mod board;
#[cfg(feature = "board_rocket_chip")]
#[path = "board/rocket_chip/mod.rs"]
pub mod board;
#[cfg(not(any(feature = "board_u540", feature = "board_rocket_chip")))]
#[cfg(not(feature = "board_u540"))]
#[path = "board/virt/mod.rs"]
pub mod board;
@ -34,9 +31,6 @@ pub extern "C" fn rust_main(hartid: usize, device_tree_paddr: usize) -> ! {
cpu::set_cpu_id(hartid);
}
#[cfg(feature = "board_rocket_chip")]
let device_tree_vaddr = board::DTB.as_ptr() as usize;
if hartid != BOOT_HART_ID {
while !AP_CAN_INIT.load(Ordering::Relaxed) {}
println!(
@ -92,33 +86,6 @@ const BOOT_HART_ID: usize = 0;
#[cfg(feature = "board_u540")]
const BOOT_HART_ID: usize = 1;
// Constant & Macro for `trap.asm`
#[cfg(target_arch = "riscv32")]
global_asm!(
r"
.equ XLENB, 4
.equ XLENb, 32
.macro LOAD a1, a2
lw \a1, \a2*XLENB(sp)
.endm
.macro STORE a1, a2
sw \a1, \a2*XLENB(sp)
.endm
"
);
#[cfg(target_arch = "riscv64")]
global_asm!(
r"
.equ XLENB, 8
.equ XLENb, 64
.macro LOAD a1, a2
ld \a1, \a2*XLENB(sp)
.endm
.macro STORE a1, a2
sd \a1, \a2*XLENB(sp)
.endm
"
);
#[cfg(target_arch = "riscv32")]
global_asm!(include_str!("boot/entry32.asm"));
#[cfg(all(target_arch = "riscv64", not(feature = "board_k210")))]

36
kernel/src/arch/riscv/paging.rs
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@ -206,42 +206,6 @@ impl PageTableExt for PageTableImpl {
));
table[i].set(frame, flags);
}
// MMIO range 0x60000000 - 0x7FFFFFFF does not work as a large page, dunno why
// map Uartlite for Rocket Chip
#[cfg(feature = "board_rocket_chip")]
{
let flags = EF::VALID | EF::READABLE | EF::WRITABLE;
self.page_table
.map_to(
Page::of_addr(VirtAddr::new(PHYSICAL_MEMORY_OFFSET + 0x6000_0000)),
Frame::of_addr(PhysAddr::new(0x6000_0000)),
flags,
&mut FrameAllocatorForRiscv,
)
.unwrap()
.flush();
// map AXI INTC for Rocket Chip
self.page_table
.map_to(
Page::of_addr(VirtAddr::new(PHYSICAL_MEMORY_OFFSET + 0x6120_0000)),
Frame::of_addr(PhysAddr::new(0x6120_0000)),
flags,
&mut FrameAllocatorForRiscv,
)
.unwrap()
.flush();
// map AXI4-Stream Data FIFO for Rocket Chip
self.page_table
.map_to(
Page::of_addr(VirtAddr::new(PHYSICAL_MEMORY_OFFSET + 0x64A0_0000)),
Frame::of_addr(PhysAddr::new(0x64A0_0000)),
flags,
&mut FrameAllocatorForRiscv,
)
.unwrap()
.flush();
}
}
fn token(&self) -> usize {

2
kernel/src/arch/x86_64/signal.rs
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@ -1,4 +1,4 @@
use crate::arch::interrupt::TrapFrame;
use trapframe::TrapFrame;
#[repr(C)]
#[derive(Clone, Debug)]

9
kernel/src/shell.rs
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@ -13,17 +13,8 @@ pub fn add_user_shell() {
// This one can transfer env vars!
// Why???
// #[cfg(target_arch = "x86_64")]
// let init_shell="/bin/busybox"; // from alpine linux
//
// #[cfg(not(target_arch = "x86_64"))]
#[cfg(not(feature = "board_rocket_chip"))]
let init_shell = "/busybox"; //from docker-library
// fd is not available on rocket chip
#[cfg(feature = "board_rocket_chip")]
let init_shell = "/rust/sh";
#[cfg(target_arch = "x86_64")]
let init_envs: Vec<String> =
vec!["PATH=/usr/sbin:/usr/bin:/sbin:/bin:/usr/x86_64-alpine-linux-musl/bin".into()];