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1,151 Commits 6 Branches 1 Tag 15 MiB
75ba0859cf
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Author SHA1 Message Date
Harry Chen
75ba0859cf Run cargo fmt 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-09 17:08:04 +08:00
Harry Chen
9b5f7b8078 Use host gcc for preprocessing in makefile 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-09 17:06:33 +08:00
Harry Chen
801b2e609a Fix makefile for aarch64 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-09 16:16:09 +08:00
Harry Chen
782da8761d Fix travis config (forget in last commit) 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-09 13:51:34 +08:00
Harry Chen
aa9bf593e2 Fix Makefile for aarch64, install dtc in travis config 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-09 13:47:04 +08:00
Harry Chen
4fc32572b0 Fix some review problems, add mispel arch to CI 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-09 13:31:56 +08:00
Harry Chen
37a69c2a47 Update user repo to latest version, ready for first merge 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-09 12:34:30 +08:00
Harry Chen
358e682bad Enable PCI initialization for matal, update mips crate and user app repo 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-09 01:08:49 +08:00
Yuhao Zhou
067d4d1193 Merge branch 'mipsel' of github.com:oscourse-tsinghua/rcore_plus into mipsel 2019-04-08 22:36:15 +08:00
Yuhao Zhou
9078190e28 Fix many bugs. 
* timer counter overflow
* clear TLB when switching context
* fix cp0.ebase access (sel = 1)
* clear TLB when editing page table
 2019-04-08 22:35:02 +08:00
Harry Chen
39a4dd2ff0 Fix VGA driver, now screen lightens on malta! 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-08 20:53:14 +08:00
Yuhao Zhou
2baf15acac Update kstack switch. 2019-04-08 14:29:27 +08:00
Yuhao Zhou
4a81242552 Fix kstack switch. 2019-04-08 12:50:30 +08:00
Yuhao Zhou
248623096b Merge branch 'mipsel' of github.com:oscourse-tsinghua/rcore_plus into mipsel 2019-04-08 04:49:22 +08:00
Yuhao Zhou
b6aa9858d3 Fix return register in sys_clone. 2019-04-08 04:47:36 +08:00
Harry Chen
7e3d26ce6b Add debug output for qemu vga driver, still not working... 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-08 03:59:42 +08:00
Harry Chen
a57a22a26b Fix VGA initialization with correct PCI address 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-08 03:18:31 +08:00
Harry Chen
8754a6eb15 Add PCI initialization in QEMU stdvga 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-08 03:03:35 +08:00
Harry Chen
c32b0d6bee Add VGA implementation for mipsel malta board 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-08 02:06:30 +08:00
Harry Chen
4e72c66087 Merge branch 'mipsel' of github.com:oscourse-tsinghua/rcore_plus into mipsel 2019-04-08 01:45:57 +08:00
Harry Chen
df3eb0e1da Add ColorConfig support to framebuffer driver 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-08 01:30:25 +08:00
Yuhao Zhou
684a2c5dd8 Fix syscall return register. 2019-04-08 01:00:26 +08:00
Harry Chen
12598a07bf Update to latest user app 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-07 18:59:09 +08:00
Harry Chen
706f7e4e9a Fix UART controller for malta, now input works! 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-07 18:52:10 +08:00
Harry Chen
ecdbc9fd7a Switch to uart2 on malta to get interrupts (not working) 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-07 18:36:29 +08:00
Harry Chen
b1fa65b9c9 Use syscall from MIPS o32 ABI, read boot command line in dts from 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-07 18:04:28 +08:00
Harry Chen
88bda7c4a0 Use Linux syscall number for mips N32 ABI, update user app 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-07 17:08:03 +08:00
Harry Chen
a0f298f6dd Use MIPS N32 abi for syscall handling 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-07 16:21:15 +08:00
Yuhao Zhou
9d576b4827 Update Cargo.lock for rust-mips. 2019-04-07 04:21:35 +08:00
Yuhao Zhou
da8d32c0cf Update syscall convention. 2019-04-07 04:20:17 +08:00
Yuhao Zhou
94d4d01cd5 Merge branch 'mipsel' of github.com:oscourse-tsinghua/rcore_plus into mipsel 2019-04-07 02:46:21 +08:00
Yuhao Zhou
f535073fbc Support user thread. 2019-04-07 02:45:41 +08:00
Harry Chen
bb123add18 Eliminate multiple warnings, update user app repo 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-07 01:32:32 +08:00
Yuhao Zhou
fbc421ee4c Fix trapframe size. 2019-04-06 23:50:05 +08:00
Harry Chen
a2e98d73fd Extract serial driver and add mipssim board for mipsel 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-06 21:59:16 +08:00
Yuhao Zhou
3d083eec0c Fix pgfault handler. 2019-04-06 21:08:36 +08:00
Yuhao Zhou
5e44304f74 Fix root page table ptr/buffer. 2019-04-06 20:26:10 +08:00
Yuhao Zhou
1f8b73744c Disable multi-CPU. 2019-04-06 19:26:14 +08:00
Harry Chen
bb374ba4bd Mock a Mutex for serial on thinpad 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-06 17:17:20 +08:00
Harry Chen
fedb53346a Update mips crate 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-06 15:46:08 +08:00
Harry Chen
62fe4e5361 Update rust-mips crate 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-06 14:45:28 +08:00
Harry Chen
48864bd79b Add more output to backtrace, revert fs change, update rust-mips 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-06 14:43:10 +08:00
Harry Chen
d05c4cf09e Merge branch 'mipsel' of github.com:oscourse-tsinghua/rcore_plus into mipsel 2019-04-06 14:17:24 +08:00
Harry Chen
b75e388aa1 Fix backtrace for mipsel 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-06 14:15:55 +08:00
Yuhao Zhou
6038004576 Add page table lookup in pagefault. 2019-04-06 11:59:22 +08:00
Harry Chen
6cc607e0c8 Make aarch64 and mipsel use img instead of qcow 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-06 11:20:50 +08:00
Yuhao Zhou
9a9e8048cb Move text base to higher location to avoid colliding with qemu BIOS 2019-04-06 03:22:26 +08:00
Yuhao Zhou
fb08410cb5 Fix paging bug. 2019-04-06 02:46:40 +08:00
Harry Chen
6e2947ac56 Fix uart address definition on thinpad 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-06 02:43:00 +08:00
Harry Chen
96caa80914 Extract some board-specfic constants 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-06 02:20:49 +08:00