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https://github.com/rcore-os/rCore.git
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Merge branch 'mipsel' of github.com:oscourse-tsinghua/rcore_plus into mipsel
This commit is contained in:
commit
94d4d01cd5
@ -12,7 +12,6 @@ pub mod driver;
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use log::*;
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use mips::registers::cp0;
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use mips::instructions;
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#[cfg(feature = "board_malta")]
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#[path = "board/malta/mod.rs"]
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@ -40,7 +39,6 @@ pub extern fn rust_main() -> ! {
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let ebase = cp0::ebase::read_u32();
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let cpu_id = ebase & 0x3ff;
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let dtb_start = _dtb_start as usize;
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let dtb_end = _dtb_end as usize;
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if cpu_id != BOOT_CPU_ID {
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// TODO: run others_main on other CPU
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@ -1,5 +1,7 @@
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//! 16550 serial adapter driver for malta board
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#![allow(dead_code)]
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use core::fmt::{Write, Result, Arguments};
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use core::ptr::{read_volatile, write_volatile};
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use spin::Mutex;
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@ -216,7 +216,7 @@ impl MutexSupport for Spin {
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unsafe {
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#[cfg(target_arch = "x86_64")]
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asm!("pause" :::: "volatile");
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#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
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#[cfg(any(target_arch = "riscv32", target_arch = "riscv64", target_arch = "mips"))]
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asm!("nop" :::: "volatile");
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#[cfg(target_arch = "aarch64")]
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asm!("yield" :::: "volatile");
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@ -254,7 +254,7 @@ impl MutexSupport for SpinNoIrq {
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unsafe {
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#[cfg(target_arch = "x86_64")]
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asm!("pause" :::: "volatile");
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#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
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#[cfg(any(target_arch = "riscv32", target_arch = "riscv64", target_arch = "mips"))]
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asm!("nop" :::: "volatile");
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#[cfg(target_arch = "aarch64")]
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asm!("yield" :::: "volatile");
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2
user
2
user
@ -1 +1 @@
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Subproject commit 67890aeb4205083d5a95b1f70de92ae39b549c8c
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Subproject commit a460c5b32744292ed50922a159fa22c830aa61b9
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