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https://github.com/rcore-os/rCore.git
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Fix some review problems, add mispel arch to CI
Signed-off-by: Harry Chen <i@harrychen.xyz>
This commit is contained in:
parent
37a69c2a47
commit
4fc32572b0
10
.travis.yml
10
.travis.yml
@ -28,6 +28,7 @@ env:
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- ARCH="riscv32"
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- ARCH="x86_64"
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- ARCH="aarch64"
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- ARCH="mipsel" OPTS="board=malta"
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matrix:
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allow_failures:
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@ -90,6 +91,15 @@ install:
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export PATH=$PATH:$PWD/riscv64-linux-musl-cross/bin;
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fi;
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fi
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- if [ $ARCH = mipsel ]; then
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if [ $TRAVIS_OS_NAME = linux ]; then
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sudo apt update;
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sudo apt install linux-headers-$(uname -r);
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wget https://musl.cc/mipsel-linux-musln32-cross.tgz;
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tar -xvf mipsel-linux-musln32-cross.tgz;
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export PATH=$PATH:$PWD/mipsel-linux-musln32-cross/bin;
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fi;
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fi
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before_script:
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@ -136,7 +136,7 @@ qemu_opts += \
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else ifeq ($(arch), mipsel)
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ifeq ($(board), malta)
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qemu_opts += \
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-machine $(board) \
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-machine $(board) -device VGA \
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-serial null -serial null -serial mon:stdio \
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-kernel $(kernel_img)
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endif
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@ -1,72 +0,0 @@
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--- atomic_backup.rs 2018-10-06 19:59:14.000000000 +0800
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+++ atomic.rs 2018-10-26 14:34:31.000000000 +0800
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@@ -125,6 +125,9 @@
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#[cfg(target_has_atomic = "8")]
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#[stable(feature = "rust1", since = "1.0.0")]
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pub struct AtomicBool {
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+ #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
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+ v: UnsafeCell<u32>,
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+ #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
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v: UnsafeCell<u8>,
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}
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@@ -265,6 +268,59 @@
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pub const ATOMIC_BOOL_INIT: AtomicBool = AtomicBool::new(false);
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#[cfg(target_has_atomic = "8")]
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+#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
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+impl AtomicBool {
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+ ///
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+ #[inline]
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+ #[stable(feature = "rust1", since = "1.0.0")]
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+ pub const fn new(v: bool) -> AtomicBool {
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+ AtomicBool { v: UnsafeCell::new(v as u32) }
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+ }
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+
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+ ///
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+ #[inline]
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+ #[stable(feature = "rust1", since = "1.0.0")]
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+ pub fn load(&self, order: Ordering) -> bool {
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+ unsafe { atomic_load(self.v.get(), order) != 0 }
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+ }
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+
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+ ///
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+ #[inline]
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+ #[stable(feature = "rust1", since = "1.0.0")]
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+ pub fn store(&self, val: bool, order: Ordering) {
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+ unsafe { atomic_store(self.v.get(), val as u32, order); }
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+ }
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+
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+ ///
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+ #[inline]
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+ #[stable(feature = "rust1", since = "1.0.0")]
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+ pub fn compare_and_swap(&self, current: bool, new: bool, order: Ordering) -> bool {
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+ match self.compare_exchange(current, new, order, strongest_failure_ordering(order)) {
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+ Ok(x) => x,
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+ Err(x) => x,
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+ }
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+ }
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+
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+ ///
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+ #[inline]
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+ #[stable(feature = "extended_compare_and_swap", since = "1.10.0")]
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+ pub fn compare_exchange(&self,
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+ current: bool,
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+ new: bool,
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+ success: Ordering,
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+ failure: Ordering)
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+ -> Result<bool, bool> {
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+ match unsafe {
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+ atomic_compare_exchange(self.v.get(), current as u32, new as u32, success, failure)
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+ } {
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+ Ok(x) => Ok(x != 0),
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+ Err(x) => Err(x != 0),
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+ }
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+ }
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+}
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+
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+#[cfg(target_has_atomic = "8")]
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+#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
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impl AtomicBool {
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/// Creates a new `AtomicBool`.
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///
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@ -1,6 +1,6 @@
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#include "regdef.h"
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.set noreorder
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.set noreorder
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.section .text.entry
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.globl _start
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.extern _root_page_table_buffer
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@ -8,12 +8,12 @@
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_start:
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# setup stack and gp
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la sp, bootstacktop
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la sp, bootstacktop
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la gp, _gp
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la t0, _cur_kstack_ptr
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la t1, _root_page_table_buffer
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sw t1, 0(t0)
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la t0, _cur_kstack_ptr
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la t1, _root_page_table_buffer
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sw t1, 0(t0)
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# set ebase
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la t0, trap_entry
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