mirror of
https://github.com/rcore-os/rCore.git
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51 lines
2.0 KiB
Markdown
51 lines
2.0 KiB
Markdown
# RustOS
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[](https://travis-ci.org/wangrunji0408/RustOS)
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Rust port for uCore OS, supporting x86_64 and riscv32i.
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[Dev docs](https://rucore.gitbook.io/rust-os-docs/) (in Chinese)
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## Summary
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This is a project of THU Operating System (2018 Spring) && Comprehensive Experiment of Computer System (2018 Summer).
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Project wiki (internal access only): [OS](http://os.cs.tsinghua.edu.cn/oscourse/OS2018spring/projects/g11), [CECS](http://os.cs.tsinghua.edu.cn/oscourse/csproject2018/group05)
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Reports (in Chinese): [MidReport](./docs/MidReport.md), [FinalReport](./docs/FinalReport.md), [RISCV port note](./docs/RISCV.md)
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The initial goal is to write a mini OS in Rust with multi-core support. More specifically, it would start from the post of the [Writing an OS in Rust](http://os.phil-opp.com) series, then reimplement [xv6-x86_64](https://github.com/jserv/xv6-x86_64) in Rust style.
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In fact, it's more complicated than we expected to write an OS starting from scratch. So by the end of OS course, we only finished rewriting [ucore_os_lab](https://github.com/chyyuu/ucore_os_lab), without multi-core support. Then as a part of [CECS project](https://github.com/riscv-and-rust-and-decaf), we ported it from x86_64 to RISCV32I, and made it work on our FPGA CPU.
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## Building
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### Environment
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* [Rust](https://www.rust-lang.org) toolchain at nightly-2018-09-18
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* Cargo tools: [cargo-xbuild](https://github.com/rust-osdev/cargo-xbuild), [bootimage](https://github.com/rust-osdev/bootimage)
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* QEMU >= 2.12.0
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* [RISCV64 GNU toolchain](https://www.sifive.com/products/tools/) (for riscv32)
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### How to run
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```bash
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rustup component add rust-src
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cargo install cargo-xbuild bootimage
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```
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```bash
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git clone https://github.com/wangrunji0408/RustOS.git
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cd RustOS/kernel
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rustup override set nightly-2018-09-18
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make run arch=riscv32|x86_64
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# For FPGA:
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# make run arch=riscv32 board=1
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```
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## License
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The source code is dual-licensed under MIT or the Apache License (Version 2.0).
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