Temporary commit for cleanup.

kernel/Cargo.lock

@@ -89,9 +89,9 @@ dependencies = [
 
 [[package]]
 name = "bit-vec"
-version = "0.6.2"
+version = "0.6.3"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "5f0dc55f2d8a1a85650ac47858bb001b4c0dd73d79e3c455a842925e68d29cd3"
+checksum = "349f9b6a179ed607305526ca489b34ad0a41aed5f7980fa90eb03160b69598fb"
 
 [[package]]
 name = "bit_field"
@@ -164,9 +164,9 @@ dependencies = [
 
 [[package]]
 name = "cc"
-version = "1.0.60"
+version = "1.0.67"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "ef611cc68ff783f18535d77ddd080185275713d852c4f5cbb6122c462a7a825c"
+checksum = "e3c69b077ad434294d3ce9f1f6143a2a4b89a8a2d54ef813d85003a4fd1137fd"
 
 [[package]]
 name = "cfg-if"
@@ -504,7 +504,7 @@ dependencies = [
  "rcore-fs-ramfs",
  "rcore-fs-sfs",
  "rcore-memory",
- "riscv 0.5.6 (git+https://github.com/rcore-os/riscv?rev=38f3786)",
+ "riscv",
  "rlibc",
  "rvm",
  "smoltcp",
@@ -618,19 +618,7 @@ dependencies = [
 
 [[package]]
 name = "riscv"
-version = "0.5.6"
+version = "0.6.0"
-source = "git+https://github.com/rcore-os/riscv?rev=38f3786#38f3786966ba15cc76977375162e3f3622a30f4b"
-dependencies = [
- "bare-metal",
- "bit_field 0.10.1",
- "bitflags",
- "log",
- "riscv-target",
-]
-
-[[package]]
-name = "riscv"
-version = "0.5.6"
 dependencies = [
  "bare-metal",
  "bit_field 0.10.1",
@@ -687,7 +675,7 @@ dependencies = [
  "log",
  "numeric-enum-macro",
  "raw-cpuid",
- "riscv 0.5.6",
+ "riscv",
  "rvm_macros",
  "spin",
  "x86",

kernel/Cargo.toml

@@ -19,7 +19,7 @@ authors = [
 ]
 
 [features]
-default = ["hypervisor"]
+default = []
 board_qemu = []
 board_u540 = ["link_user"]
 # (for aarch64 RaspberryPi3)
@@ -88,7 +88,7 @@ uart_16550 = "0.2.7"
 x86_64 = "0.11"
 
 [target.'cfg(any(target_arch = "riscv32", target_arch = "riscv64"))'.dependencies]
-riscv = { git = "https://github.com/rcore-os/riscv", rev = "38f3786", features = ["inline-asm"] }
+riscv = { path = "../submodules/riscv" ,  features = ["inline-asm", "hypervisor"] }
 
 [target.'cfg(target_arch = "aarch64")'.dependencies]
 aarch64 = { git = "https://github.com/rcore-os/aarch64", version = "3.0.1" }

kernel/Makefile

@@ -127,6 +127,7 @@ qemu_opts += \
 else
 qemu_opts += \
 	-machine virt \
+	-cpu rv64,x-h=true \
 	-serial mon:stdio \
 	-bios ../tools/opensbi/fw_jump.elf  \
 	-device loader,addr=0x80200000,file=$(kernel_img) \
@@ -257,6 +258,8 @@ debug: $(kernel) $(kernel_img)
 	@sleep 1
 	@$(gdb) $(kernel) -x ../tools/gdbinit
 
+justdebug:
+	@$(qemu) $(qemu_opts) -s -S
 build: $(kernel_img)
 
 asm:

kernel/src/arch/riscv/interrupt/mod.rs

@@ -36,6 +36,11 @@ pub unsafe fn restore(flags: usize) {
 /// This function is called from `trap.asm`.
 #[no_mangle]
 pub extern "C" fn trap_handler(tf: &mut TrapFrame) {
+    trap_handler_no_frame(&mut tf.sepc);
+}
+
+#[inline]
+pub fn trap_handler_no_frame(sepc: &mut usize) {
     use self::scause::{Exception as E, Interrupt as I, Trap};
     let scause = scause::read();
     let stval = stval::read();
@@ -44,9 +49,9 @@ pub extern "C" fn trap_handler(tf: &mut TrapFrame) {
         Trap::Interrupt(I::SupervisorExternal) => external(),
         Trap::Interrupt(I::SupervisorSoft) => ipi(),
         Trap::Interrupt(I::SupervisorTimer) => timer(),
-        Trap::Exception(E::LoadPageFault) => page_fault(stval, tf),
+        Trap::Exception(E::LoadPageFault) => page_fault(stval, sepc),
-        Trap::Exception(E::StorePageFault) => page_fault(stval, tf),
+        Trap::Exception(E::StorePageFault) => page_fault(stval, sepc),
-        Trap::Exception(E::InstructionPageFault) => page_fault(stval, tf),
+        Trap::Exception(E::InstructionPageFault) => page_fault(stval, sepc),
         _ => panic!("unhandled trap {:?}", scause.cause()),
     }
     trace!("Interrupt end");
@@ -73,9 +78,9 @@ pub fn timer() {
     crate::trap::timer();
 }
 
-fn page_fault(stval: usize, tf: &mut TrapFrame) {
+fn page_fault(stval: usize, sepc: &mut usize) {
     let addr = stval;
-    trace!("\nEXCEPTION: Page Fault @ {:#x}", addr);
+    info!("\nEXCEPTION: Page Fault @ {:#x}", addr);
 
     if crate::memory::handle_page_fault(addr) {
         return;
@@ -84,9 +89,9 @@ fn page_fault(stval: usize, tf: &mut TrapFrame) {
         fn _copy_user_start();
         fn _copy_user_end();
     }
-    if tf.sepc >= _copy_user_start as usize && tf.sepc < _copy_user_end as usize {
+    if *sepc >= _copy_user_start as usize && *sepc < _copy_user_end as usize {
-        debug!("fixup for addr {:x?}", addr);
+        info!("fixup for addr {:x?}", addr);
-        tf.sepc = crate::memory::read_user_fixup as usize;
+        *sepc = crate::memory::read_user_fixup as usize;
         return;
     }
     panic!("unhandled page fault");

kernel/src/arch/riscv/paging.rs

@@ -5,7 +5,9 @@ use log::*;
 use rcore_memory::paging::*;
 use riscv::addr::*;
 use riscv::asm::{sfence_vma, sfence_vma_all};
-use riscv::paging::{FrameAllocator, FrameDeallocator};
+use riscv::paging::MapperFlushable;
+use riscv::paging::PTE;
+use riscv::paging::{FrameAllocatorFor, FrameDeallocatorFor};
 use riscv::paging::{Mapper, PageTable as RvPageTable, PageTableEntry, PageTableFlags as EF};
 use riscv::register::satp;
 
@@ -14,6 +16,13 @@ type TopLevelPageTable<'a> = riscv::paging::Rv32PageTable<'a>;
 #[cfg(target_arch = "riscv64")]
 type TopLevelPageTable<'a> = riscv::paging::Rv39PageTable<'a>;
 
+use riscv::use_sv32;
+use riscv::use_sv39;
+#[cfg(target_arch = "riscv32")]
+use_sv32!();
+#[cfg(target_arch = "riscv64")]
+use_sv39!();
+
 pub struct PageTableImpl {
     page_table: TopLevelPageTable<'static>,
     root_frame: Frame,
@@ -29,7 +38,7 @@ impl PageTable for PageTableImpl {
         // map the 4K `page` to the 4K `frame` with `flags`
         let flags = EF::VALID | EF::READABLE | EF::WRITABLE;
         let page = Page::of_addr(VirtAddr::new(addr));
-        let frame = Frame::of_addr(PhysAddr::new(target));
+        let frame = Frame::of_addr(PhysAddr::new_u64(target as u64));
         // we may need frame allocator to alloc frame for new page table(first/second)
         self.page_table
             .map_to(page, frame, flags, &mut FrameAllocatorForRiscv)
@@ -99,11 +108,11 @@ impl Entry for PageEntry {
         self.0.flags_mut().set(EF::VALID | EF::READABLE, value);
     }
     fn target(&self) -> usize {
-        self.0.addr().as_usize()
+        self.0.addr::<PhysAddr>().as_usize()
     }
     fn set_target(&mut self, target: usize) {
         let flags = self.0.flags();
-        let frame = Frame::of_addr(PhysAddr::new(target));
+        let frame = Frame::of_addr(PhysAddr::new_u64(target as u64));
         self.0.set(frame, flags);
     }
     fn writable_shared(&self) -> bool {
@@ -153,7 +162,7 @@ impl PageTableImpl {
         #[cfg(target_arch = "riscv64")]
         let mask = 0x0fffffff_ffffffff;
         let frame = Frame::of_ppn(PageTableImpl::active_token() & mask);
-        let table = frame.as_kernel_mut(PHYSICAL_MEMORY_OFFSET);
+        let table = frame.as_kernel_mut(PHYSICAL_MEMORY_OFFSET as u64);
         ManuallyDrop::new(PageTableImpl {
             page_table: TopLevelPageTable::new(table, PHYSICAL_MEMORY_OFFSET),
             root_frame: frame,
@@ -170,7 +179,7 @@ impl PageTableImpl {
 impl PageTableExt for PageTableImpl {
     fn new_bare() -> Self {
         let target = alloc_frame().expect("failed to allocate frame");
-        let frame = Frame::of_addr(PhysAddr::new(target));
+        let frame = Frame::of_addr(PhysAddr::new_u64(target as u64));
 
         let table = unsafe { &mut *(phys_to_virt(target) as *mut RvPageTable) };
         table.zero();
@@ -202,8 +211,8 @@ impl PageTableExt for PageTableImpl {
             }
             let flags =
                 EF::VALID | EF::READABLE | EF::WRITABLE | EF::EXECUTABLE | EF::ACCESSED | EF::DIRTY;
-            let frame = Frame::of_addr(PhysAddr::new(
+            let frame = Frame::of_addr(PhysAddr::new_u64(
-                (0xFFFFFF80_00000000 + (i << 30)) - PHYSICAL_MEMORY_OFFSET,
+                ((0xFFFFFF80_00000000 + (i << 30)) - PHYSICAL_MEMORY_OFFSET) as u64,
             ));
             table[i].set(frame, flags);
         }
@@ -239,13 +248,13 @@ impl Drop for PageTableImpl {
 
 struct FrameAllocatorForRiscv;
 
-impl FrameAllocator for FrameAllocatorForRiscv {
+impl FrameAllocatorFor<PhysAddr> for FrameAllocatorForRiscv {
     fn alloc(&mut self) -> Option<Frame> {
-        alloc_frame().map(|addr| Frame::of_addr(PhysAddr::new(addr)))
+        alloc_frame().map(|addr| Frame::of_addr(PhysAddr::new_u64(addr as u64)))
     }
 }
 
-impl FrameDeallocator for FrameAllocatorForRiscv {
+impl FrameDeallocatorFor<PhysAddr> for FrameAllocatorForRiscv {
     fn dealloc(&mut self, frame: Frame) {
         dealloc_frame(frame.start_address().as_usize());
     }

kernel/src/arch/riscv/timer.rs

@@ -39,5 +39,5 @@ pub fn set_next() {
 
 pub fn timer_now() -> Duration {
     let time = get_cycle();
-    Duration::from_nanos(time * 100 )
+    Duration::from_nanos(time * 100)
 }

kernel/src/rvm/memory.rs

@@ -85,6 +85,7 @@ impl<T: FrameAllocator> MemoryHandler for RvmPageTableHandlerDelay<T> {
         if target == 0 {
             target = self.allocator.alloc().expect("failed to alloc frame");
         }
+        info!("guest_paddr={}, target={}", guest_paddr, target);
         rvm_pt
             .map(guest_paddr, target, GuestMemoryAttr::default())
             .expect("failed to create GPA -> HPA mapping");

kernel/src/rvm/mod.rs

@@ -38,6 +38,16 @@ mod rvm_extern_fn {
     fn rvm_dealloc_frame(paddr: usize) {
         dealloc_frame(paddr)
     }
+    #[rvm::extern_fn(alloc_frame_x4)]
+    fn rvm_alloc_frame_x4() -> Option<usize> {
+        use crate::memory::alloc_frame_contiguous;
+        alloc_frame_contiguous(4, 2)
+    }
+
+    #[rvm::extern_fn(dealloc_frame_x4)]
+    fn rvm_dealloc_frame_x4(paddr: usize) {
+        dealloc_frame(paddr)
+    }
 
     #[rvm::extern_fn(phys_to_virt)]
     fn rvm_phys_to_virt(paddr: usize) -> usize {
@@ -52,4 +62,27 @@ mod rvm_extern_fn {
         }
         __alltraps as usize
     }
+
+    #[cfg(any(target_arch = "riscv64", target_arch = "riscv32"))]
+    #[rvm::extern_fn(riscv_trap_handler_no_frame)]
+    fn rvm_riscv_trap_handler_no_frame(sepc: &mut usize) {
+        crate::arch::interrupt::trap_handler_no_frame(sepc);
+    }
+
+    #[cfg(all(
+        any(target_arch = "riscv64", target_arch = "riscv32"),
+        feature = "hypervisor"
+    ))]
+    #[rvm::extern_fn(riscv_check_hypervisor_extension)]
+    fn rvm_riscv_check_hypervisor_extension() -> bool {
+        return true;
+    }
+    #[cfg(all(
+        any(target_arch = "riscv64", target_arch = "riscv32"),
+        not(feature = "hypervisor")
+    ))]
+    #[rvm::extern_fn(riscv_check_hypervisor_extension)]
+    fn rvm_riscv_check_hypervisor_extension() -> bool {
+        return false;
+    }
 }

kernel/src/trap.rs

@@ -3,24 +3,23 @@ use crate::consts::INFORM_PER_MSEC;
 use crate::process::*;
 use crate::sync::SpinNoIrqLock as Mutex;
 use crate::{signal::SignalUserContext, sync::Condvar};
+use core::sync::atomic::{AtomicUsize, Ordering};
 use core::time::Duration;
 use naive_timer::Timer;
 use trapframe::TrapFrame;
 use trapframe::UserContext;
-use core::sync::atomic::{Ordering, AtomicUsize};
 pub static TICK: AtomicUsize = AtomicUsize::new(0);
 pub static TICK_ALL_PROCESSORS: AtomicUsize = AtomicUsize::new(0);
 
-pub unsafe fn wall_tick()->usize{
+pub unsafe fn wall_tick() -> usize {
     return TICK.load(Ordering::Relaxed);
 }
-pub fn cpu_tick()->usize{
+pub fn cpu_tick() -> usize {
     return TICK_ALL_PROCESSORS.load(Ordering::Relaxed);
 }
-pub fn do_tick(){
+pub fn do_tick() {
     if crate::arch::cpu::id() == 0 {
-        let ret=TICK.fetch_add(1, Ordering::Relaxed);
+        let ret = TICK.fetch_add(1, Ordering::Relaxed);
-        
     }
     TICK_ALL_PROCESSORS.fetch_add(1, Ordering::Relaxed);
 }
@@ -39,7 +38,7 @@ lazy_static! {
 pub fn timer() {
     do_tick();
     //let ret=unsafe{wall_tick()};
-    
+
     let now = crate::arch::timer::timer_now();
     NAIVE_TIMER.lock().expire(now);
 }