submodules.

.gitmodules

@@ -7,3 +7,12 @@
 [submodule "submodules/rcore-fs"]
 	path = submodules/rcore-fs
 	url = https://github.com/rcore-os/rcore-fs
+[submodule "submodules/RVM"]
+	path = submodules/RVM
+	url = https://github.com/rcore-riscv-hypervisor-dev/RVM
+[submodule "submodules/riscv"]
+	path = submodules/riscv
+	url = https://github.com/rcore-riscv-hypervisor-dev/riscv
+[submodule "submodules/riscv-hypervisor-extension"]
+	path = submodules/riscv-hypervisor-extension
+	url = https://github.com/rcore-riscv-hypervisor-dev/riscv-hypervisor-extension

kernel/Cargo.lock

@@ -504,7 +504,7 @@ dependencies = [
  "rcore-fs-ramfs",
  "rcore-fs-sfs",
  "rcore-memory",
- "riscv",
+ "riscv 0.5.6 (git+https://github.com/rcore-os/riscv?rev=38f3786)",
  "rlibc",
  "rvm",
  "smoltcp",
@@ -628,6 +628,17 @@ dependencies = [
  "riscv-target",
 ]
 
+[[package]]
+name = "riscv"
+version = "0.5.6"
+dependencies = [
+ "bare-metal",
+ "bit_field 0.10.1",
+ "bitflags",
+ "log",
+ "riscv-target",
+]
+
 [[package]]
 name = "riscv-target"
 version = "0.1.2"
@@ -667,7 +678,6 @@ dependencies = [
 [[package]]
 name = "rvm"
 version = "1.0.1"
-source = "git+https://github.com/rcore-os/RVM?rev=939eb0a#939eb0aafd100e9944e4f2fe90eebfa8149d2b85"
 dependencies = [
  "bit-set",
  "bit_field 0.10.1",
@@ -677,6 +687,7 @@ dependencies = [
  "log",
  "numeric-enum-macro",
  "raw-cpuid",
+ "riscv 0.5.6",
  "rvm_macros",
  "spin",
  "x86",
@@ -686,7 +697,6 @@ dependencies = [
 [[package]]
 name = "rvm_macros"
 version = "0.1.0"
-source = "git+https://github.com/rcore-os/RVM?rev=939eb0a#939eb0aafd100e9944e4f2fe90eebfa8149d2b85"
 dependencies = [
  "quote",
  "syn",

kernel/Cargo.toml

@@ -19,7 +19,7 @@ authors = [
 ]
 
 [features]
-default = []
+default = ["hypervisor"]
 board_qemu = []
 board_u540 = ["link_user"]
 # (for aarch64 RaspberryPi3)
@@ -76,7 +76,7 @@ virtio-drivers = { git = "https://github.com/rcore-os/virtio-drivers", rev = "df
 volatile = "0.2"
 woke = "0.0.2"
 xmas-elf = "0.7"
-rvm = { git = "https://github.com/rcore-os/RVM", rev = "939eb0a", optional = true }
+rvm = { path = "../submodules/RVM", optional = true }
 
 [target.'cfg(target_arch = "x86_64")'.dependencies]
 apic = { git = "https://github.com/rcore-os/apic-rs", rev = "fb86bd7" }

kernel/src/trap.rs

@@ -20,9 +20,6 @@ pub fn cpu_tick()->usize{
 pub fn do_tick(){
     if crate::arch::cpu::id() == 0 {
         let ret=TICK.fetch_add(1, Ordering::Relaxed);
-        if ret%100==0{
-            info!("{}", ret);
-        }
         
     }
     TICK_ALL_PROCESSORS.fetch_add(1, Ordering::Relaxed);

submodules/RVM

@@ -0,0 +1 @@
+Subproject commit 024d95bd307ae65ebdcc8ec69ed113b3b2fd6155

submodules/riscv

@@ -0,0 +1 @@
+Subproject commit 5b88df3698906d0926949a8f8917a1d68ac12b99

submodules/riscv-hypervisor-extension

@@ -0,0 +1 @@
+Subproject commit 88f03d4c6d806a1359ae9d095ab284d609aeeabe