diff --git a/kernel/src/arch/aarch64/fp.rs b/kernel/src/arch/aarch64/fp.rs new file mode 100644 index 00000000..c2a8a884 --- /dev/null +++ b/kernel/src/arch/aarch64/fp.rs @@ -0,0 +1,12 @@ +#[derive(Debug, Copy, Clone, Default)] +pub struct FpState {} + +impl FpState { + pub fn new() -> Self { + Self { ..Self::default() } + } + + pub fn save(&mut self) {} + + pub fn restore(&self) {} +} diff --git a/kernel/src/arch/aarch64/mod.rs b/kernel/src/arch/aarch64/mod.rs index 9ea9a9ee..50314983 100644 --- a/kernel/src/arch/aarch64/mod.rs +++ b/kernel/src/arch/aarch64/mod.rs @@ -5,6 +5,7 @@ use core::sync::atomic::{spin_loop_hint, AtomicBool, Ordering}; mod boot; pub mod consts; pub mod cpu; +pub mod fp; pub mod interrupt; pub mod io; pub mod memory; diff --git a/kernel/src/arch/aarch64/signal.rs b/kernel/src/arch/aarch64/signal.rs index b4136b7b..60e4ff7a 100644 --- a/kernel/src/arch/aarch64/signal.rs +++ b/kernel/src/arch/aarch64/signal.rs @@ -1,40 +1,121 @@ -use trapframe::TrapFrame; +use trapframe::UserContext; +// mcontext #[repr(C)] #[derive(Clone, Debug)] pub struct MachineContext { - pub r8: usize, - pub r9: usize, - pub r10: usize, - pub r11: usize, - pub r12: usize, - pub r13: usize, - pub r14: usize, - pub r15: usize, - pub rdi: usize, - pub rsi: usize, - pub rbp: usize, - pub rbx: usize, - pub rdx: usize, - pub rax: usize, - pub rcx: usize, - pub rsp: usize, - pub rip: usize, - pub eflags: usize, - pub cs: u16, - pub gs: u16, - pub fs: u16, - pub _pad: u16, - pub err: usize, - pub trapno: usize, - pub oldmask: usize, - pub cr2: usize, - pub fpstate: usize, - pub _reserved1: [usize; 8], + fault_address: usize, + x0: usize, + x1: usize, + x2: usize, + x3: usize, + x4: usize, + x5: usize, + x6: usize, + x7: usize, + x8: usize, + x9: usize, + x10: usize, + x11: usize, + x12: usize, + x13: usize, + x14: usize, + x15: usize, + x16: usize, + x17: usize, + x18: usize, + x19: usize, + x20: usize, + x21: usize, + x22: usize, + x23: usize, + x24: usize, + x25: usize, + x26: usize, + x27: usize, + x28: usize, + x29: usize, + x30: usize, + sp: usize, + pc: usize, + pstate: usize, } impl MachineContext { - pub fn from_tf(tf: &TrapFrame) -> Self { - todo!() + pub fn from_tf(tf: &UserContext) -> Self { + Self { + fault_address: 0, + x0: tf.general.x0, + x1: tf.general.x1, + x2: tf.general.x2, + x3: tf.general.x3, + x4: tf.general.x4, + x5: tf.general.x5, + x6: tf.general.x6, + x7: tf.general.x7, + x8: tf.general.x8, + x9: tf.general.x9, + x10: tf.general.x10, + x11: tf.general.x13, + x12: tf.general.x12, + x13: tf.general.x13, + x14: tf.general.x14, + x15: tf.general.x15, + x16: tf.general.x16, + x17: tf.general.x17, + x18: tf.general.x18, + x19: tf.general.x19, + x20: tf.general.x20, + x21: tf.general.x21, + x22: tf.general.x22, + x23: tf.general.x23, + x24: tf.general.x24, + x25: tf.general.x25, + x26: tf.general.x26, + x27: tf.general.x27, + x28: tf.general.x28, + x29: tf.general.x29, + x30: tf.general.x30, + sp: tf.sp, + pc: tf.elr, + pstate: tf.spsr, + } + } + + pub fn fill_tf(&self, tf: &mut UserContext) { + tf.general.x0 = self.x0; + tf.general.x1 = self.x1; + tf.general.x2 = self.x2; + tf.general.x3 = self.x3; + tf.general.x4 = self.x4; + tf.general.x5 = self.x5; + tf.general.x6 = self.x6; + tf.general.x7 = self.x7; + tf.general.x8 = self.x8; + tf.general.x9 = self.x9; + tf.general.x10 = self.x10; + tf.general.x11 = self.x11; + tf.general.x12 = self.x12; + tf.general.x13 = self.x13; + tf.general.x14 = self.x14; + tf.general.x15 = self.x15; + tf.general.x16 = self.x16; + tf.general.x17 = self.x17; + tf.general.x18 = self.x18; + tf.general.x19 = self.x19; + tf.general.x20 = self.x20; + tf.general.x21 = self.x21; + tf.general.x22 = self.x22; + tf.general.x23 = self.x23; + tf.general.x24 = self.x24; + tf.general.x25 = self.x25; + tf.general.x26 = self.x26; + tf.general.x27 = self.x27; + tf.general.x28 = self.x28; + tf.general.x29 = self.x29; + tf.general.x30 = self.x30; + tf.sp = self.sp; + tf.elr = self.pc; + tf.spsr = self.pstate; } } diff --git a/kernel/src/drivers/mmc/bcm2835_sdhci.rs b/kernel/src/drivers/mmc/bcm2835_sdhci.rs index 762bc6d8..c5689410 100644 --- a/kernel/src/drivers/mmc/bcm2835_sdhci.rs +++ b/kernel/src/drivers/mmc/bcm2835_sdhci.rs @@ -15,25 +15,25 @@ use core::time::Duration; pub const BLOCK_SIZE: usize = 512; const SD_CMD_TYPE_NORMAL: u32 = 0x0; -const SD_CMD_TYPE_SUSPEND: u32 = (1 << 22); -const SD_CMD_TYPE_RESUME: u32 = (2 << 22); -const SD_CMD_TYPE_ABORT: u32 = (3 << 22); -const SD_CMD_TYPE_MASK: u32 = (3 << 22); -const SD_CMD_ISDATA: u32 = (1 << 21); -const SD_CMD_IXCHK_EN: u32 = (1 << 20); -const SD_CMD_CRCCHK_EN: u32 = (1 << 19); +const SD_CMD_TYPE_SUSPEND: u32 = 1 << 22; +const SD_CMD_TYPE_RESUME: u32 = 2 << 22; +const SD_CMD_TYPE_ABORT: u32 = 3 << 22; +const SD_CMD_TYPE_MASK: u32 = 3 << 22; +const SD_CMD_ISDATA: u32 = 1 << 21; +const SD_CMD_IXCHK_EN: u32 = 1 << 20; +const SD_CMD_CRCCHK_EN: u32 = 1 << 19; const SD_CMD_RSPNS_TYPE_NONE: u32 = 0; // For no response -const SD_CMD_RSPNS_TYPE_136: u32 = (1 << 16); // For response R2 (with CRC), R3,4 (no CRC) -const SD_CMD_RSPNS_TYPE_48: u32 = (2 << 16); // For responses R1, R5, R6, R7 (with CRC) -const SD_CMD_RSPNS_TYPE_48B: u32 = (3 << 16); // For responses R1b, R5b (with CRC) -const SD_CMD_RSPNS_TYPE_MASK: u32 = (3 << 16); -const SD_CMD_MULTI_BLOCK: u32 = (1 << 5); +const SD_CMD_RSPNS_TYPE_136: u32 = 1 << 16; // For response R2 (with CRC), R3,4 (no CRC) +const SD_CMD_RSPNS_TYPE_48: u32 = 2 << 16; // For responses R1, R5, R6, R7 (with CRC) +const SD_CMD_RSPNS_TYPE_48B: u32 = 3 << 16; // For responses R1b, R5b (with CRC) +const SD_CMD_RSPNS_TYPE_MASK: u32 = 3 << 16; +const SD_CMD_MULTI_BLOCK: u32 = 1 << 5; const SD_CMD_DAT_DIR_HC: u32 = 0; -const SD_CMD_DAT_DIR_CH: u32 = (1 << 4); +const SD_CMD_DAT_DIR_CH: u32 = 1 << 4; const SD_CMD_AUTO_CMD_EN_NONE: u32 = 0; -const SD_CMD_AUTO_CMD_EN_CMD12: u32 = (1 << 2); -const SD_CMD_AUTO_CMD_EN_CMD23: u32 = (2 << 2); -const SD_CMD_BLKCNT_EN: u32 = (1 << 1); +const SD_CMD_AUTO_CMD_EN_CMD12: u32 = 1 << 2; +const SD_CMD_AUTO_CMD_EN_CMD23: u32 = 2 << 2; +const SD_CMD_BLKCNT_EN: u32 = 1 << 1; const SD_CMD_DMA: u32 = 1; const SD_ERR_BASE: u32 = 16; @@ -50,13 +50,13 @@ const SD_ERR_ADMA: u32 = 9; // !(not supported) const SD_ERR_TUNING: u32 = 10; // !(not supported) const SD_ERR_RSVD: u32 = 11; // !(not supported) -const SD_ERR_MASK_CMD_TIMEOUT: u32 = (1 << (16 + SD_ERR_CMD_TIMEOUT)); -const SD_ERR_MASK_CMD_CRC: u32 = (1 << (16 + SD_ERR_CMD_CRC)); -const SD_ERR_MASK_CMD_END_BIT: u32 = (1 << (16 + SD_ERR_CMD_END_BIT)); -const SD_ERR_MASK_CMD_INDEX: u32 = (1 << (16 + SD_ERR_CMD_INDEX)); -const SD_ERR_MASK_DATA_TIMEOUT: u32 = (1 << (16 + SD_ERR_CMD_TIMEOUT)); -const SD_ERR_MASK_DATA_CRC: u32 = (1 << (16 + SD_ERR_CMD_CRC)); -const SD_ERR_MASK_DATA_END_BIT: u32 = (1 << (16 + SD_ERR_CMD_END_BIT)); +const SD_ERR_MASK_CMD_TIMEOUT: u32 = 1 << (16 + SD_ERR_CMD_TIMEOUT); +const SD_ERR_MASK_CMD_CRC: u32 = 1 << (16 + SD_ERR_CMD_CRC); +const SD_ERR_MASK_CMD_END_BIT: u32 = 1 << (16 + SD_ERR_CMD_END_BIT); +const SD_ERR_MASK_CMD_INDEX: u32 = 1 << (16 + SD_ERR_CMD_INDEX); +const SD_ERR_MASK_DATA_TIMEOUT: u32 = 1 << (16 + SD_ERR_CMD_TIMEOUT); +const SD_ERR_MASK_DATA_CRC: u32 = 1 << (16 + SD_ERR_CMD_CRC); +const SD_ERR_MASK_DATA_END_BIT: u32 = 1 << (16 + SD_ERR_CMD_END_BIT); // const SD_ERR_MASK_CURRENT_LIMIT: u32 = (1 << (16 + SD_ERR_CMD_CURRENT_LIMIT)); // const SD_ERR_MASK_AUTO_CMD12: u32 = (1 << (16 + SD_ERR_CMD_AUTO_CMD12)); // const SD_ERR_MASK_ADMA: u32 = (1 << (16 + SD_ERR_CMD_ADMA)); @@ -73,18 +73,18 @@ const SD_CARD_REMOVAL: u32 = 1 << 7; const SD_CARD_INTERRUPT: u32 = 1 << 8; const SD_RESP_NONE: u32 = SD_CMD_RSPNS_TYPE_NONE; -const SD_RESP_R1: u32 = (SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN); -const SD_RESP_R1b: u32 = (SD_CMD_RSPNS_TYPE_48B | SD_CMD_CRCCHK_EN); -const SD_RESP_R2: u32 = (SD_CMD_RSPNS_TYPE_136 | SD_CMD_CRCCHK_EN); +const SD_RESP_R1: u32 = SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN; +const SD_RESP_R1b: u32 = SD_CMD_RSPNS_TYPE_48B | SD_CMD_CRCCHK_EN; +const SD_RESP_R2: u32 = SD_CMD_RSPNS_TYPE_136 | SD_CMD_CRCCHK_EN; const SD_RESP_R3: u32 = SD_CMD_RSPNS_TYPE_48; const SD_RESP_R4: u32 = SD_CMD_RSPNS_TYPE_136; -const SD_RESP_R5: u32 = (SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN); -const SD_RESP_R5b: u32 = (SD_CMD_RSPNS_TYPE_48B | SD_CMD_CRCCHK_EN); -const SD_RESP_R6: u32 = (SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN); -const SD_RESP_R7: u32 = (SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN); +const SD_RESP_R5: u32 = SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN; +const SD_RESP_R5b: u32 = SD_CMD_RSPNS_TYPE_48B | SD_CMD_CRCCHK_EN; +const SD_RESP_R6: u32 = SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN; +const SD_RESP_R7: u32 = SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN; -const SD_DATA_READ: u32 = (SD_CMD_ISDATA | SD_CMD_DAT_DIR_CH); -const SD_DATA_WRITE: u32 = (SD_CMD_ISDATA | SD_CMD_DAT_DIR_HC); +const SD_DATA_READ: u32 = SD_CMD_ISDATA | SD_CMD_DAT_DIR_CH; +const SD_DATA_WRITE: u32 = SD_CMD_ISDATA | SD_CMD_DAT_DIR_HC; const SD_VER_UNKNOWN: u32 = 0; const SD_VER_1: u32 = 1; @@ -277,17 +277,17 @@ macro_rules! ACMD { (($a) | (IS_APP_CMD)) }; } -const SET_BUS_WIDTH: u32 = (6 | IS_APP_CMD); -const SD_STATUS: u32 = (13 | IS_APP_CMD); -const SEND_NUM_WR_BLOCKS: u32 = (22 | IS_APP_CMD); -const SET_WR_BLK_ERASE_COUNT: u32 = (23 | IS_APP_CMD); -const SD_SEND_OP_COND: u32 = (41 | IS_APP_CMD); -const SET_CLR_CARD_DETECT: u32 = (42 | IS_APP_CMD); -const SEND_SCR: u32 = (51 | IS_APP_CMD); +const SET_BUS_WIDTH: u32 = 6 | IS_APP_CMD; +const SD_STATUS: u32 = 13 | IS_APP_CMD; +const SEND_NUM_WR_BLOCKS: u32 = 22 | IS_APP_CMD; +const SET_WR_BLK_ERASE_COUNT: u32 = 23 | IS_APP_CMD; +const SD_SEND_OP_COND: u32 = 41 | IS_APP_CMD; +const SET_CLR_CARD_DETECT: u32 = 42 | IS_APP_CMD; +const SEND_SCR: u32 = 51 | IS_APP_CMD; -const SD_RESET_CMD: u32 = (1 << 25); -const SD_RESET_DAT: u32 = (1 << 26); -const SD_RESET_ALL: u32 = (1 << 24); +const SD_RESET_CMD: u32 = 1 << 25; +const SD_RESET_DAT: u32 = 1 << 26; +const SD_RESET_ALL: u32 = 1 << 24; #[repr(C)] #[derive(Debug)] @@ -483,15 +483,10 @@ impl EmmcCtl { } pub fn sd_get_clock_divider(&mut self, base_clock: u32, target_rate: u32) -> u32 { - let targetted_divisor: u32 = if (target_rate > base_clock) { + let targetted_divisor: u32 = if target_rate > base_clock { 1 } else { - base_clock / target_rate - - if (base_clock % target_rate != 0) { - 1 - } else { - 0 - } + base_clock / target_rate - if base_clock % target_rate != 0 { 1 } else { 0 } }; let mut divisor = 31; @@ -548,7 +543,7 @@ impl EmmcCtl { usleep(2000); // Enable the SD clock - control1 |= (1 << 2); + control1 |= 1 << 2; self.emmc.registers.CONTROL1.write(control1); usleep(2000); @@ -776,7 +771,7 @@ impl EmmcCtl { ); if self.sd_issue_command_int_pre(command, 0, timeout) { let mut buf = &mut self.sd_scr.scr; - let mut wr_irpt = (1 << 5); + let mut wr_irpt = 1 << 5; let mut finished = true; for cur_block in 0..count { timeout_wait!( @@ -793,7 +788,7 @@ impl EmmcCtl { break; } let mut cur_word_no = 0; - while (cur_word_no < blocks_size_u32) { + while cur_word_no < blocks_size_u32 { let word = self.emmc.registers.DATA.read(); debug!( "EmmcCtl: block#{}, word#{} = 0x{:08X}, pos = {}", @@ -886,7 +881,7 @@ impl EmmcCtl { let mut control0 = self.emmc.registers.CONTROL0.read(); let mut control1 = self.emmc.registers.CONTROL1.read(); - control1 |= (1 << 24); + control1 |= 1 << 24; // Disable clock control1 &= !(1 << 2); control1 &= !(1 << 0); @@ -919,7 +914,7 @@ impl EmmcCtl { let f_id = self.sd_get_clock_divider(base_clock, 400000); control1 |= f_id; - control1 |= (7 << 16); // data timeout = TMCLK * 2^10 + control1 |= 7 << 16; // data timeout = TMCLK * 2^10 self.emmc.registers.CONTROL1.write(control1); @@ -1006,9 +1001,9 @@ impl EmmcCtl { while card_is_busy { let v2_flags = if v2_later { - (1 << 30) + 1 << 30 | if self.failed_voltage_switch == 0 { - (1 << 24) + 1 << 24 } else { 0 } @@ -1043,7 +1038,7 @@ impl EmmcCtl { // Switch to 1.8V mode if possible debug!("EmmcCtl: card_supports_18v = {}", self.card_supports_18v); - if (self.card_supports_18v) { + if self.card_supports_18v { // As per HCSS 3.6.1 debug!("EmmcCtl: Switch to 1.8v mode."); // Send VOLTAGE_SWITCH @@ -1068,7 +1063,7 @@ impl EmmcCtl { // Set 1.8V signal enable to 1 control0 = self.emmc.registers.CONTROL0.read(); - control0 |= (1 << 8); + control0 |= 1 << 8; self.emmc.registers.CONTROL0.write(control0); usleep(5000); @@ -1083,7 +1078,7 @@ impl EmmcCtl { // Re-enable SD clock control1 = self.emmc.registers.CONTROL1.read(); - control1 |= (1 << 2); + control1 |= 1 << 2; self.emmc.registers.CONTROL1.write(control1); // Wait 1 ms @@ -1170,7 +1165,7 @@ impl EmmcCtl { self.block_size = 512; let mut controller_block_size = self.emmc.registers.BLKSIZECNT.read(); - controller_block_size &= (!0xfff); + controller_block_size &= !0xfff; controller_block_size |= 0x200; self.emmc.registers.BLKSIZECNT.write(controller_block_size); @@ -1292,7 +1287,7 @@ impl EmmcCtl { // send command self.last_cmd = command; if self.sd_issue_command_int_pre(sd_commands[command as usize], block_no, 500000) { - let mut wr_irpt = (1 << 5); + let mut wr_irpt = 1 << 5; let mut finished = true; for cur_block in 0..count { timeout_wait!( @@ -1308,7 +1303,7 @@ impl EmmcCtl { break; } let mut cur_word_no = 0; - while (cur_word_no < blocks_size_u32) { + while cur_word_no < blocks_size_u32 { buf[(cur_block as usize) * blocks_size_u32 + cur_word_no] = self.emmc.registers.DATA.read(); cur_word_no += 1; @@ -1350,7 +1345,7 @@ impl EmmcCtl { // send command self.last_cmd = command; if self.sd_issue_command_int_pre(sd_commands[command as usize], block_no, 500000) { - let mut wr_irpt = (1 << 4); + let mut wr_irpt = 1 << 4; let mut finished = true; for cur_block in 0..count { timeout_wait!( @@ -1366,7 +1361,7 @@ impl EmmcCtl { break; } let mut cur_word_no = 0; - while (cur_word_no < blocks_size_u32) { + while cur_word_no < blocks_size_u32 { self.emmc .registers .DATA diff --git a/kernel/src/lib.rs b/kernel/src/lib.rs index b8cd4cc2..a6ee0f76 100644 --- a/kernel/src/lib.rs +++ b/kernel/src/lib.rs @@ -13,11 +13,14 @@ #![deny(stable_features)] #![deny(unused_unsafe)] #![deny(ellipsis_inclusive_range_patterns)] +#![deny(unused_parens)] #![allow(non_upper_case_globals)] #![allow(dead_code)] #![allow(unused_mut)] #![allow(unused_variables)] #![allow(unused_imports)] +#![allow(unreachable_patterns)] +#![allow(unused_assignments)] #![no_std] // just keep it ... diff --git a/kernel/src/syscall/mod.rs b/kernel/src/syscall/mod.rs index adfe71d8..9d91c3c9 100644 --- a/kernel/src/syscall/mod.rs +++ b/kernel/src/syscall/mod.rs @@ -335,7 +335,6 @@ impl Syscall<'_> { ) .await } - #[cfg(target_arch = "x86_64")] SYS_TKILL => self.sys_tkill(args[0], args[1]), // time