From 4fc32572b06afa933eda8cd68089ad3cdcfe82cc Mon Sep 17 00:00:00 2001
From: Harry Chen <i@harrychen.xyz>
Date: Tue, 9 Apr 2019 13:31:56 +0800
Subject: [PATCH] Fix some review problems, add mispel arch to CI

Signed-off-by: Harry Chen <i@harrychen.xyz>
---
 .travis.yml                         | 10 ++++
 kernel/Makefile                     |  2 +-
 kernel/src/arch/mipsel/atomic.patch | 72 -----------------------------
 kernel/src/arch/mipsel/boot/entry.S | 10 ++--
 4 files changed, 16 insertions(+), 78 deletions(-)
 delete mode 100644 kernel/src/arch/mipsel/atomic.patch

diff --git a/.travis.yml b/.travis.yml
index e7ecc381..58f2acf5 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -28,6 +28,7 @@ env:
     - ARCH="riscv32"
     - ARCH="x86_64"
     - ARCH="aarch64"
+    - ARCH="mipsel" OPTS="board=malta"
 
 matrix:
     allow_failures:
@@ -90,6 +91,15 @@ install:
     export PATH=$PATH:$PWD/riscv64-linux-musl-cross/bin;
     fi;
     fi
+  - if [ $ARCH = mipsel ]; then
+    if [ $TRAVIS_OS_NAME = linux ]; then
+    sudo apt update;
+    sudo apt install linux-headers-$(uname -r);
+    wget https://musl.cc/mipsel-linux-musln32-cross.tgz;
+    tar -xvf mipsel-linux-musln32-cross.tgz;
+    export PATH=$PATH:$PWD/mipsel-linux-musln32-cross/bin;
+    fi;
+    fi
 
 
 before_script:
diff --git a/kernel/Makefile b/kernel/Makefile
index 2db02a5f..d85eed86 100644
--- a/kernel/Makefile
+++ b/kernel/Makefile
@@ -136,7 +136,7 @@ qemu_opts += \
 else ifeq ($(arch), mipsel)
 ifeq ($(board), malta)
 qemu_opts += \
-	-machine $(board) \
+	-machine $(board) -device VGA \
 	-serial null -serial null -serial mon:stdio \
 	-kernel $(kernel_img)
 endif
diff --git a/kernel/src/arch/mipsel/atomic.patch b/kernel/src/arch/mipsel/atomic.patch
deleted file mode 100644
index d7722b6f..00000000
--- a/kernel/src/arch/mipsel/atomic.patch
+++ /dev/null
@@ -1,72 +0,0 @@
---- atomic_backup.rs	2018-10-06 19:59:14.000000000 +0800
-+++ atomic.rs	2018-10-26 14:34:31.000000000 +0800
-@@ -125,6 +125,9 @@
- #[cfg(target_has_atomic = "8")]
- #[stable(feature = "rust1", since = "1.0.0")]
- pub struct AtomicBool {
-+    #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
-+    v: UnsafeCell<u32>,
-+    #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
-     v: UnsafeCell<u8>,
- }
- 
-@@ -265,6 +268,59 @@
- pub const ATOMIC_BOOL_INIT: AtomicBool = AtomicBool::new(false);
- 
- #[cfg(target_has_atomic = "8")]
-+#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
-+impl AtomicBool {
-+    ///
-+    #[inline]
-+    #[stable(feature = "rust1", since = "1.0.0")]
-+    pub const fn new(v: bool) -> AtomicBool {
-+        AtomicBool { v: UnsafeCell::new(v as u32) }
-+    }
-+
-+    ///
-+    #[inline]
-+    #[stable(feature = "rust1", since = "1.0.0")]
-+    pub fn load(&self, order: Ordering) -> bool {
-+        unsafe { atomic_load(self.v.get(), order) != 0 }
-+    }
-+
-+    ///
-+    #[inline]
-+    #[stable(feature = "rust1", since = "1.0.0")]
-+    pub fn store(&self, val: bool, order: Ordering) {
-+        unsafe { atomic_store(self.v.get(), val as u32, order); }
-+    }
-+
-+    ///
-+    #[inline]
-+    #[stable(feature = "rust1", since = "1.0.0")]
-+    pub fn compare_and_swap(&self, current: bool, new: bool, order: Ordering) -> bool {
-+        match self.compare_exchange(current, new, order, strongest_failure_ordering(order)) {
-+            Ok(x) => x,
-+            Err(x) => x,
-+        }
-+    }
-+
-+    ///
-+    #[inline]
-+    #[stable(feature = "extended_compare_and_swap", since = "1.10.0")]
-+    pub fn compare_exchange(&self,
-+                            current: bool,
-+                            new: bool,
-+                            success: Ordering,
-+                            failure: Ordering)
-+                            -> Result<bool, bool> {
-+        match unsafe {
-+            atomic_compare_exchange(self.v.get(), current as u32, new as u32, success, failure)
-+        } {
-+            Ok(x) => Ok(x != 0),
-+            Err(x) => Err(x != 0),
-+        }
-+    }
-+}
-+
-+#[cfg(target_has_atomic = "8")]
-+#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
- impl AtomicBool {
-     /// Creates a new `AtomicBool`.
-     ///
diff --git a/kernel/src/arch/mipsel/boot/entry.S b/kernel/src/arch/mipsel/boot/entry.S
index 0e45ba7e..e72c353b 100644
--- a/kernel/src/arch/mipsel/boot/entry.S
+++ b/kernel/src/arch/mipsel/boot/entry.S
@@ -1,6 +1,6 @@
 #include "regdef.h"
 
-	.set noreorder
+    .set noreorder
     .section .text.entry
     .globl _start
 	.extern _root_page_table_buffer
@@ -8,12 +8,12 @@
 
 _start:
     # setup stack and gp
-	la    sp, bootstacktop
+    la    sp, bootstacktop
     la    gp, _gp
 
-	la    t0, _cur_kstack_ptr
-	la    t1, _root_page_table_buffer
-	sw    t1, 0(t0)
+    la    t0, _cur_kstack_ptr
+    la    t1, _root_page_table_buffer
+    sw    t1, 0(t0)
 
     # set ebase
     la    t0, trap_entry