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Move arch specific code to arch
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8822964045
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README.md
10
README.md
@ -8,10 +8,10 @@ Going to be the next generation teaching operating system.
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Supported architectures and boards:
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Supported architectures and boards:
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* x86_64: QEMU, PC (i5/i7)
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* x86_64(Tier 1): QEMU, PC (i5/i7)
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* RISCV32/64: QEMU, HiFive Unleashed
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* RISCV32/64(Tier 2): QEMU, HiFive Unleashed
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* AArch64: QEMU, Raspberry Pi 3B+
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* AArch64(Tier 2): QEMU, Raspberry Pi 3B+
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* MIPS32: QEMU, [TrivialMIPS](https://github.com/Harry-Chen/TrivialMIPS)
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* MIPS32(Tier 3): QEMU, [TrivialMIPS](https://github.com/Harry-Chen/TrivialMIPS)
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![demo](./docs/2_OSLab/os2atc/demo.png)
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![demo](./docs/2_OSLab/os2atc/demo.png)
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@ -74,7 +74,7 @@ See [Makefile](kernel/Makefile) for more usages.
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This is a project of THU courses:
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This is a project of THU courses:
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* [Operating System (2018 Spring) ](http://os.cs.tsinghua.edu.cn/oscourse/OS2018spring/projects/g11)
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* [Operating System (2018 Spring)](http://os.cs.tsinghua.edu.cn/oscourse/OS2018spring/projects/g11)
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* [Comprehensive Experiment of Computer System (2018 Summer)](http://os.cs.tsinghua.edu.cn/oscourse/csproject2018/group05)
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* [Comprehensive Experiment of Computer System (2018 Summer)](http://os.cs.tsinghua.edu.cn/oscourse/csproject2018/group05)
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* [Operating System Train (2018 Autumn)](http://os.cs.tsinghua.edu.cn/oscourse/OsTrain2018)
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* [Operating System Train (2018 Autumn)](http://os.cs.tsinghua.edu.cn/oscourse/OsTrain2018)
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* [Operating System (2019 Spring)](http://os.cs.tsinghua.edu.cn/oscourse/OS2019spring/projects)
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* [Operating System (2019 Spring)](http://os.cs.tsinghua.edu.cn/oscourse/OS2019spring/projects)
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@ -145,6 +145,7 @@ qemu_net_opts += \
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-device virtio-net-device,netdev=net0
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-device virtio-net-device,netdev=net0
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else ifeq ($(ARCH), aarch64)
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else ifeq ($(ARCH), aarch64)
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# raspi must have at least 4 cpus
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qemu_opts += \
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qemu_opts += \
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-machine $(BOARD) \
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-machine $(BOARD) \
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-smp 4 \
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-smp 4 \
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@ -63,3 +63,9 @@
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### fp
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### fp
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- struct FpState:浮点的状态
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- struct FpState:浮点的状态
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### signal
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- struct MachineContext:和 Linux 中的 mcontext 一致
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- RETCODE:调用 rt_sigreturn syscall 的指令
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- set_signal_handler:设置 signal handler
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@ -1,3 +1,5 @@
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//! SPDX-License-Identifier: (Apache-2.0 OR MIT)
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#[derive(Debug, Copy, Clone, Default)]
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#[derive(Debug, Copy, Clone, Default)]
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pub struct FpState {}
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pub struct FpState {}
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@ -1,3 +1,5 @@
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use crate::signal::Siginfo;
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use crate::signal::SignalUserContext;
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use trapframe::UserContext;
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use trapframe::UserContext;
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// mcontext
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// mcontext
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@ -119,3 +121,23 @@ impl MachineContext {
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tf.spsr = self.pstate;
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tf.spsr = self.pstate;
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}
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}
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}
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}
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// TODO
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pub const RET_CODE: [u8; 7] = [0; 7];
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pub fn set_signal_handler(
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tf: &mut UserContext,
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sp: usize,
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handler: usize,
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signo: usize,
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siginfo: *const Siginfo,
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ucontext: *const SignalUserContext,
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) {
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tf.sp = sp;
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tf.elr = handler;
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// pass handler argument
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tf.general.x0 = signo as usize;
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tf.general.x1 = siginfo as usize;
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tf.general.x2 = ucontext as usize;
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}
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@ -1,3 +1,5 @@
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use crate::signal::Siginfo;
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use crate::signal::SignalUserContext;
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use trapframe::UserContext;
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use trapframe::UserContext;
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// mcontext_t
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// mcontext_t
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@ -79,3 +81,23 @@ impl MachineContext {
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pub fn fill_tf(&self, ctx: &mut UserContext) {}
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pub fn fill_tf(&self, ctx: &mut UserContext) {}
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}
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}
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// TODO
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pub const RET_CODE: [u8; 7] = [0; 7];
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pub fn set_signal_handler(
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tf: &mut UserContext,
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sp: usize,
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handler: usize,
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signo: usize,
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siginfo: *const Siginfo,
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ucontext: *const SignalUserContext,
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) {
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tf.general.sp = sp;
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tf.sepc = handler;
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// pass handler argument
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tf.general.a0 = signo as usize;
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tf.general.a1 = siginfo as usize;
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tf.general.a2 = ucontext as usize;
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}
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@ -1,3 +1,4 @@
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use crate::signal::{Siginfo, SignalUserContext};
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use trapframe::{GeneralRegs, UserContext};
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use trapframe::{GeneralRegs, UserContext};
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/// struct mcontext
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/// struct mcontext
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@ -95,3 +96,27 @@ impl MachineContext {
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ctx.error_code = self.err;
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ctx.error_code = self.err;
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}
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}
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}
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}
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pub const RET_CODE: [u8; 7] = [
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// mov SYS_RT_SIGRETURN, %eax
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0xb8, // SYS_RT_SIGRETURN
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15, 0, 0, 0, // syscall
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0x0f, 0x05,
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];
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pub fn set_signal_handler(
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tf: &mut UserContext,
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sp: usize,
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handler: usize,
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signo: usize,
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siginfo: *const Siginfo,
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ucontext: *const SignalUserContext,
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) {
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tf.general.rsp = sp;
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tf.general.rip = handler;
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// pass handler argument
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tf.general.rdi = signo as usize;
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tf.general.rsi = siginfo as usize;
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tf.general.rdx = ucontext as usize;
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}
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@ -1,3 +1,4 @@
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//! Provide backtrace upon panic
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use core::mem::size_of;
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use core::mem::size_of;
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extern "C" {
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extern "C" {
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@ -1,5 +1,4 @@
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#![allow(dead_code)]
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//! Global constants
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pub use crate::arch::consts::*;
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pub use crate::arch::consts::*;
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pub const MAX_CPU_NUM: usize = 64;
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pub const MAX_CPU_NUM: usize = 64;
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//! Define the FrameAllocator for physical memory
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//! Define the FrameAllocator for physical memory
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//! x86_64 -- 64GB
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//! AARCH64/MIPS/RV -- 1GB
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//! NOTICE:
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//! type FrameAlloc = bitmap_allocator::BitAllocXXX
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//! KSTACK_SIZE -- 16KB
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//!
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//! KERNEL_HEAP_SIZE:
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//! x86-64 -- 32MB
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//! AARCH64/RV64 -- 8MB
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//! MIPS/RV32 -- 2MB
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//! mipssim/malta(MIPS) -- 10MB
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use super::HEAP_ALLOCATOR;
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use super::HEAP_ALLOCATOR;
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pub use crate::arch::paging::*;
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use crate::consts::{KERNEL_OFFSET, MEMORY_OFFSET, PHYSICAL_MEMORY_OFFSET};
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use crate::consts::{KERNEL_OFFSET, MEMORY_OFFSET, PHYSICAL_MEMORY_OFFSET};
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use crate::process::current_thread;
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use crate::process::current_thread;
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use crate::sync::SpinNoIrqLock;
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use crate::sync::SpinNoIrqLock;
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use core::mem;
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use core::mem;
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use core::mem::size_of;
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use core::mem::size_of;
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use log::*;
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use log::*;
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pub use rcore_memory::memory_set::{handler::*, MemoryArea, MemoryAttr};
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use rcore_memory::*;
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use rcore_memory::*;
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pub use crate::arch::paging::*;
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pub use rcore_memory::memory_set::{handler::*, MemoryArea, MemoryAttr};
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pub type MemorySet = rcore_memory::memory_set::MemorySet<PageTableImpl>;
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pub type MemorySet = rcore_memory::memory_set::MemorySet<PageTableImpl>;
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// x86_64 support up to 1T memory
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// x86_64 support up to 1T memory
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use crate::arch::{signal::MachineContext, syscall::SYS_RT_SIGRETURN};
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use crate::arch::{
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signal::{set_signal_handler, MachineContext, RET_CODE},
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syscall::SYS_RT_SIGRETURN,
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};
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use crate::process::{process, process_of, Process, Thread};
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use crate::process::{process, process_of, Process, Thread};
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use crate::sync::{Event, MutexGuard, SpinNoIrq, SpinNoIrqLock as Mutex};
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use crate::sync::{Event, MutexGuard, SpinNoIrq, SpinNoIrqLock as Mutex};
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use alloc::sync::Arc;
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use alloc::sync::Arc;
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@ -250,25 +253,16 @@ pub fn handle_signal(thread: &Arc<Thread>, tf: &mut UserContext) -> bool {
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} else {
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} else {
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frame.ret_code_addr = frame.ret_code.as_ptr() as usize;
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frame.ret_code_addr = frame.ret_code.as_ptr() as usize;
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// mov SYS_RT_SIGRETURN, %eax
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// mov SYS_RT_SIGRETURN, %eax
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frame.ret_code[0] = 0xb8;
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frame.ret_code.copy_from_slice(&RET_CODE);
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// TODO: ref plz
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unsafe {
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*(frame.ret_code.as_ptr().add(1) as *mut u32) = SYS_RT_SIGRETURN as u32;
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}
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// syscall
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frame.ret_code[5] = 0x0f;
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frame.ret_code[6] = 0x05;
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}
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#[cfg(target_arch = "x86_64")]
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{
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tf.general.rsp = sig_sp;
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tf.general.rip = action.handler;
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// pass handler argument
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tf.general.rdi = info.signo as usize;
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tf.general.rsi = &frame.info as *const Siginfo as usize;
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tf.general.rdx = &frame.ucontext as *const SignalUserContext as usize;
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}
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}
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set_signal_handler(
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tf,
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sig_sp,
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action.handler,
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info.signo as usize,
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&frame.info as *const Siginfo,
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&frame.ucontext as *const SignalUserContext,
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);
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}
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}
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}
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}
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}
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}
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2
user
2
user
@ -1 +1 @@
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Subproject commit 84daa580e5dde1f8e16510ec1dcbdc298d13d725
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Subproject commit 291df7f66ed42f642cd691554fa0c88e59cdb894
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