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Dr. Koutheir Attouchi 2019-10-06 17:52:59 +02:00 committed by GitHub
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14
risc_v/ch1/src/asm/boot.S
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@ -44,17 +44,27 @@ _start:
# csrw medeleg, t5 # csrw medeleg, t5
# csrw mideleg, t5 # csrw mideleg, t5
la sp, _stack la sp, _stack
# We use mret here so that the mstatus register # Setting `mstatus` register:
# is properly updated. # 0b11 << 11: Machine's previous protection mode is 3 (MPP=3).
# 1 << 7 : Machine's previous interrupt-enable bit is 1 (MPIE=1).
# 1 << 3 : Machine's interrupt-enable bit is 1 (MIE=1).
li t0, (0b11 << 11) | (1 << 7) | (1 << 3) li t0, (0b11 << 11) | (1 << 7) | (1 << 3)
csrw mstatus, t0 csrw mstatus, t0
# Machine's exception program counter (MEPC) is set to `kmain`.
la t1, kmain la t1, kmain
csrw mepc, t1 csrw mepc, t1
# Machine's trap vector base address is set to `asm_trap_vector`.
la t2, asm_trap_vector la t2, asm_trap_vector
csrw mtvec, t2 csrw mtvec, t2
# Setting Machine's interrupt-enable bits (`mie` register):
# 1 << 3 : Machine's M-mode software interrupt-enable bit is 1 (MSIE=1).
# 1 << 7 : Machine's timer interrupt-enable bit is 1 (MTIE=1).
# 1 << 11: Machine's external interrupt-enable bit is 1 (MEIE=1).
li t3, (1 << 3) | (1 << 7) | (1 << 11) li t3, (1 << 3) | (1 << 7) | (1 << 11)
csrw mie, t3 csrw mie, t3
# Set the return address to infinitely wait for interrupts.
la ra, 4f la ra, 4f
# We use mret here so that the mstatus register is properly updated.
mret mret
3: 3: