diff --git a/risc_v/ch1/src/asm/boot.S b/risc_v/ch1/src/asm/boot.S
index 822881f..123d69e 100644
--- a/risc_v/ch1/src/asm/boot.S
+++ b/risc_v/ch1/src/asm/boot.S
@@ -44,17 +44,27 @@ _start:
 	# csrw	medeleg, t5
 	# csrw	mideleg, t5
 	la		sp, _stack
-	# We use mret here so that the mstatus register
-	# is properly updated.
+	# Setting `mstatus` register:
+	# 0b11 << 11: Machine's previous protection mode is 3 (MPP=3).
+	# 1 << 7    : Machine's previous interrupt-enable bit is 1 (MPIE=1).
+	# 1 << 3    : Machine's interrupt-enable bit is 1 (MIE=1).
 	li		t0, (0b11 << 11) | (1 << 7) | (1 << 3)
 	csrw	mstatus, t0
+	# Machine's exception program counter (MEPC) is set to `kmain`.
 	la		t1, kmain
 	csrw	mepc, t1
+	# Machine's trap vector base address is set to `asm_trap_vector`.
 	la		t2, asm_trap_vector
 	csrw	mtvec, t2
+	# Setting Machine's interrupt-enable bits (`mie` register):
+	# 1 << 3 : Machine's M-mode software interrupt-enable bit is 1 (MSIE=1).
+	# 1 << 7 : Machine's timer interrupt-enable bit is 1 (MTIE=1).
+	# 1 << 11: Machine's external interrupt-enable bit is 1 (MEIE=1).
 	li		t3, (1 << 3) | (1 << 7) | (1 << 11)
 	csrw	mie, t3
+	# Set the return address to infinitely wait for interrupts.
 	la		ra, 4f
+	# We use mret here so that the mstatus register is properly updated.
 	mret
 3: