mirror of
https://github.com/rcore-os/rCore.git
synced 2024-11-22 16:16:16 +04:00
84 lines
2.1 KiB
Rust
84 lines
2.1 KiB
Rust
extern crate cc;
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use std::fs::File;
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use std::io::{Result, Write};
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use std::path::Path;
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fn main() {
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println!("cargo:rerun-if-env-changed=LOG");
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println!("cargo:rerun-if-env-changed=BOARD");
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println!("cargo:rerun-if-env-changed=SFSIMG");
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let arch: String = std::env::var("ARCH").unwrap();
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let board: String = std::env::var("BOARD").unwrap();
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match arch.as_str() {
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"x86_64" => {
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gen_vector_asm().unwrap();
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}
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"riscv32" => {}
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"riscv64" => {
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if board == "rocket_chip" {
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gen_dtb_asm(&String::from("riscv32"), &board).unwrap();
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}
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}
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"mipsel" => {
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gen_dtb_asm(&arch, &board).unwrap();
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}
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"aarch64" => {}
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_ => panic!("Unknown arch {}", arch),
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}
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}
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fn gen_vector_asm() -> Result<()> {
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let mut f = File::create("src/arch/x86_64/interrupt/vector.asm").unwrap();
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writeln!(f, "# generated by build.rs - do not edit")?;
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writeln!(f, ".section .text")?;
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writeln!(f, ".intel_syntax noprefix")?;
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for i in 0..256 {
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writeln!(f, "vector{}:", i)?;
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if !(i == 8 || (i >= 10 && i <= 14) || i == 17) {
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writeln!(f, "\tpush 0")?;
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}
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writeln!(f, "\tpush {}", i)?;
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writeln!(f, "\tjmp __alltraps")?;
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}
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writeln!(f, "\n.section .rodata")?;
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writeln!(f, ".global __vectors")?;
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writeln!(f, "__vectors:")?;
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for i in 0..256 {
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writeln!(f, "\t.quad vector{}", i)?;
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}
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Ok(())
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}
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fn gen_dtb_asm(arch: &String, _board: &String) -> Result<()> {
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let dtb = std::env::var("DTB").unwrap();
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if !Path::new(&dtb).is_file() {
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panic!("DTB `{}` not found", dtb)
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}
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let mut f = File::create(format!("src/arch/{}/boot/dtb.gen.s", arch)).unwrap();
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println!("cargo:rerun-if-changed={}", dtb);
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println!("cargo:rerun-if-env-changed=DTB");
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writeln!(f, "# generated by build.rs - do not edit")?;
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write!(
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f,
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r#"
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.section .dtb,"a"
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.align 12
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.global _dtb_start, _dtb_end
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_dtb_start:
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.incbin "{}"
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_dtb_end:
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"#,
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dtb
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)?;
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Ok(())
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}
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