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rCore/user/riscv32-ucore.json
2018-12-02 19:44:05 +08:00

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{
"llvm-target": "riscv32",
"data-layout": "e-m:e-p:32:32-i64:64-n32-S128",
"target-endian": "little",
"target-pointer-width": "32",
"target-c-int-width": "32",
"os": "none",
"arch": "riscv32",
"cpu": "generic-rv32",
"features": "",
"max-atomic-width": "32",
"linker": "rust-lld",
"linker-flavor": "ld.lld",
"pre-link-args": {
"ld.lld": [
"-Tsrc/arch/riscv32/user.ld"
]
},
"executables": true,
"panic-strategy": "abort",
"relocation-model": "static",
"abi-blacklist": [
"cdecl",
"stdcall",
"fastcall",
"vectorcall",
"thiscall",
"aapcs",
"win64",
"sysv64",
"ptx-kernel",
"msp430-interrupt",
"x86-interrupt"
]
}