8 Commits

Author	SHA1	Message	Date
equation314	de6354ddd3	aarch64/mmu: use ASID to avoid flush TLB frequently in context switch	2018-11-23 23:25:15 +08:00
equation314	33d4b6975b	aarch64/mmu: use DSB instead of TLB flush after modifying PTE	2018-11-23 15:23:48 +08:00
equation314	55087fc5a2	aarch64/mmu: use both TTBR0_EL1 & TTBR1_EL1	2018-11-23 00:43:18 +08:00
equation314	bb1c1abaa4	aarch64/mmu: can run on the real raspi3	2018-11-21 20:02:34 +08:00
equation314	a9de99d3a9	aarch64/mmu: remap kernel memory ranges at the end of memory::init()	2018-11-21 01:50:34 +08:00
equation314	9e8124abbb	aarch64/mmu: mmu enabled	2018-11-20 16:46:16 +08:00
equation314	576ae1d911	add setup_page_table	2018-11-15 19:12:02 +08:00
koumingyang	ef213d60bb	mmu	2018-11-15 14:22:57 +08:00