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477 Commits 6 Branches 1 Tag 15 MiB
990ce51007
Commit Graph

69 Commits

Author SHA1 Message Date
lcy1996
990ce51007 Code Transplanting: unwrap -> expect 2018-11-08 19:58:30 +08:00
lcy1996
9adcea44d5 Code transplanting: Fix bugs. Pass test 'spin' 2018-11-08 19:21:13 +08:00
lcy1996
fcdee71f9d Merge confilt 2018-11-05 21:31:04 +08:00
lcy1996
c8ea2cb0cf Fix bug and enable swap in/out and frame delayed allocating. 2018-11-05 20:37:05 +08:00
chenqiuhao
2002ddd5fa move processor from wrj 2018-11-03 21:45:03 +08:00
lcy1996
b1425a53f9 finish frame delayed allocating 2018-11-03 14:33:36 +08:00
lcy1996
504401355f Add expr3 report(not finiished. 2018-10-30 21:50:38 +08:00
lcy1996
edde416052 Finish swap for multi-user process 2018-10-30 12:45:09 +08:00
lcy1996
ec27ed8d2e add comment 2018-10-23 00:19:37 +08:00
lcy1996
63349ade19 Finish add more comment for kernel and finish set user memory swappable. 2018-10-23 00:00:09 +08:00
lcy1996
0a81014007 Add page handler for swap in/out in riscv32's pagefault 2018-10-16 21:51:17 +08:00
Ben Pig Chu
fc727b9618 Merge branch 'OsTrain2018-g4' of https://github.com/oscourse-tsinghua/RustOS into crate-memory-comment 2018-10-09 21:42:13 +08:00
Ben Pig Chu
4a17ce8f16 comments of crate/memory 2018-10-09 21:39:34 +08:00
chenqiuhao
5bc40fd5d4 Merge branch 'OsTrain2018-g4' of https://github.com/oscourse-tsinghua/RustOS into OsTrain2018-g4 2018-10-05 12:01:21 +08:00
chenqiuhao
e05be94c80 finish the comment of the process 2018-10-05 12:01:00 +08:00
lcy1996
b3e2ca8aa0 Merge conflict 2018-10-05 11:08:50 +08:00
chenqiuhao
c4b53dc8e5 finish comment of sync 2018-10-05 09:28:17 +08:00
chenqiuhao
ddb679ce2b update comment for bbl module, but have not finished. 2018-10-04 20:56:11 +08:00
WangRunji
cd1bd55729 Update README, travis, riscv crate. 2018-09-19 20:58:00 +08:00
WangRunji
924c061d64 Merge branch 'x86-boot' 
# Conflicts:
#	crate/riscv
#	kernel/Makefile
 2018-09-19 20:18:14 +08:00
dzy
5a0ce1e464 Refactored RISC-V page table identity mapping into a function. 2018-09-14 21:44:25 +08:00
dzy
906019f7c6 Add little notes for BitAllocator 2018-09-07 20:53:37 +08:00
WangRunji
caeff9ad97 Update packages and fit for new Rust nightly 2018-09-04 13:19:23 +08:00
WangRunji
b88648ff44 Fit for newest Rust nightly. x86_64 ok, riscv32 broken. 2018-08-04 16:20:25 +08:00
WangRunji
a2111a928f Move thread mod to ucore-process crate 2018-07-17 19:06:30 +08:00
WangRunji
776dc976c9 Fix for user 2018-07-17 12:07:21 +08:00
WangRunji
06b39ed521 Impl remove any for StrideScheduler 2018-07-17 11:01:51 +08:00
WangRunji
04b62ec79f Use Vec instead of array in Scheduler 2018-07-17 02:13:42 +08:00
WangRunji
c8a9eaf3e6 Split process mod to extern crate 2018-07-17 01:56:28 +08:00
WangRunji
0c9679b710 Fix fork and syscall return value. 2018-07-15 01:07:25 +08:00
WangRunji
27daa6d491 Fix user trap 2018-07-15 00:45:53 +08:00
WangRunji
1ad3ed738e Can run user program in RV32 2018-07-14 11:56:55 +08:00
WangRunji
89bcd5f660 Fix kernel thread 2018-07-13 01:45:48 +08:00
WangRunji
96d8af8034 Use CowExt for RV32 2018-07-12 19:44:13 +08:00
WangRunji
7d856fe009 Fix memory::cow LLVM error for RV32 2018-07-12 19:35:21 +08:00
WangRunji
5530549a54 Recover process thread sync mod for RV32. Pass compile. 2018-07-12 18:56:29 +08:00
WangRunji
7c7dbc9ded Add CR3 to Context (x86_64) 2018-07-12 16:42:21 +08:00
WangRunji
95ab3a2f3b Allocate kernel stack from heap, remove stack allocator, remove guard page. 2018-07-12 00:33:43 +08:00
WangRunji
81ff6f13e5 Fix recursive mapping, finish kernel remap. 2018-07-11 23:43:28 +08:00
WangRunji
d3ed84ba61 Fix compile 2018-07-11 00:53:40 +08:00
WangRunji
aecb85d5e7 Move MemorySet out to memory crate 2018-07-10 21:54:16 +08:00
WangRunji
5c14673fe0 Setup a simple page table, enable paging. 2018-07-10 17:37:38 +08:00
WangRunji
b26fee1990 Make more mods common for both x86_64 & riscv32. 2018-07-10 17:07:03 +08:00
WangRunji
ee242b44b2 Timer interrupt 2018-07-08 01:03:33 +08:00
WangRunji
aeb7fce0e6 SBI: Support RISCV64 2018-07-08 01:02:43 +08:00
WangRunji
02b94db859 Fix crate riscv version 2018-07-07 22:59:07 +08:00
WangRunji
bf2ad7c6a5 Change target arch to RISCV32IMA. Recover some dependencies. 2018-07-06 22:33:28 +08:00
WangRunji
a44231435f Fork crate riscv as a submodule 2018-07-05 14:17:30 +08:00
WangRunji
ced765fb5b New crate bbl, port sbi mod. 2018-07-04 22:04:59 +08:00
WangRunji
98be93e215 Fix Fifo & Clock SwapManager, pass test. 2018-07-02 20:03:06 +08:00