9 Commits

Author	SHA1	Message	Date
WangRunji	b26fee1990	Make more mods common for both x86_64 & riscv32.	2018-07-10 17:07:03 +08:00
WangRunji	aa22fcabde	Change target arch to RISCV32IMA. Recover some dependencies.	2018-07-06 23:02:10 +08:00
WangRunji	c0193e69e6	Clear all code, make it compile for RISCV in docker.	2018-07-03 22:27:55 +08:00
WangRunji	f707d7e757	Fit new rust nightly. Update dependencies.	2018-06-19 23:43:40 +08:00
WangRunji	25dde04795	Tiny changes	2018-06-01 11:46:32 +08:00
WangRunji	4e35b927d2	Yield. Shorter schedule interval.	2018-05-20 17:14:05 +08:00
WangRunji	c446d2bb5e	Add test for travis	2018-04-09 21:20:47 +08:00
WangRunji	2e405a0393	Auto exit in qemu	2018-04-09 17:02:18 +08:00
WangRunji	c436b9afbe	Move asm to boot dir. Continue to refactor...	2018-04-04 20:56:56 +08:00