andrey/rCore
1
0
Fork 0
mirror of https://github.com/rcore-os/rCore.git synced 2024-11-23 08:26:17 +04:00
Code Issues Projects Releases Wiki Activity
1,406 Commits 6 Branches 1 Tag 15 MiB
7df015842d
Commit Graph

1406 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Harry Chen
7e3d26ce6b Add debug output for qemu vga driver, still not working... 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-08 03:59:42 +08:00
Harry Chen
a57a22a26b Fix VGA initialization with correct PCI address 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-08 03:18:31 +08:00
Harry Chen
8754a6eb15 Add PCI initialization in QEMU stdvga 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-08 03:03:35 +08:00
Harry Chen
c32b0d6bee Add VGA implementation for mipsel malta board 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-08 02:06:30 +08:00
Harry Chen
4e72c66087 Merge branch 'mipsel' of github.com:oscourse-tsinghua/rcore_plus into mipsel 2019-04-08 01:45:57 +08:00
Harry Chen
df3eb0e1da Add ColorConfig support to framebuffer driver 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-08 01:30:25 +08:00
Yuhao Zhou
684a2c5dd8 Fix syscall return register. 2019-04-08 01:00:26 +08:00
Harry Chen
12598a07bf Update to latest user app 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-07 18:59:09 +08:00
Harry Chen
706f7e4e9a Fix UART controller for malta, now input works! 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-07 18:52:10 +08:00
Harry Chen
ecdbc9fd7a Switch to uart2 on malta to get interrupts (not working) 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-07 18:36:29 +08:00
Harry Chen
b1fa65b9c9 Use syscall from MIPS o32 ABI, read boot command line in dts from 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-07 18:04:28 +08:00
Harry Chen
88bda7c4a0 Use Linux syscall number for mips N32 ABI, update user app 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-07 17:08:03 +08:00
Harry Chen
a0f298f6dd Use MIPS N32 abi for syscall handling 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-07 16:21:15 +08:00
Yuhao Zhou
9d576b4827 Update Cargo.lock for rust-mips. 2019-04-07 04:21:35 +08:00
Yuhao Zhou
da8d32c0cf Update syscall convention. 2019-04-07 04:20:17 +08:00
Yuhao Zhou
94d4d01cd5 Merge branch 'mipsel' of github.com:oscourse-tsinghua/rcore_plus into mipsel 2019-04-07 02:46:21 +08:00
Yuhao Zhou
f535073fbc Support user thread. 2019-04-07 02:45:41 +08:00
Jiajie Chen
2c3a4d75dd implement getaddr for netlink, ip l/ip a is working now 2019-04-07 02:19:07 +08:00
Jiajie Chen
a7a8c3aa92 implement getlink for netlink 2019-04-07 01:59:23 +08:00
Harry Chen
bb123add18 Eliminate multiple warnings, update user app repo 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-07 01:32:32 +08:00
Yuhao Zhou
fbc421ee4c Fix trapframe size. 2019-04-06 23:50:05 +08:00
Harry Chen
a2e98d73fd Extract serial driver and add mipssim board for mipsel 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-06 21:59:16 +08:00
Yuhao Zhou
3d083eec0c Fix pgfault handler. 2019-04-06 21:08:36 +08:00
Yuhao Zhou
5e44304f74 Fix root page table ptr/buffer. 2019-04-06 20:26:10 +08:00
Yuhao Zhou
1f8b73744c Disable multi-CPU. 2019-04-06 19:26:14 +08:00
Harry Chen
bb374ba4bd Mock a Mutex for serial on thinpad 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-06 17:17:20 +08:00
Harry Chen
fedb53346a Update mips crate 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-06 15:46:08 +08:00
Harry Chen
62fe4e5361 Update rust-mips crate 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-06 14:45:28 +08:00
Harry Chen
48864bd79b Add more output to backtrace, revert fs change, update rust-mips 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-06 14:43:10 +08:00
Jiajie Chen
1f99f1270a Implement recvmsg syscall for netlink 2019-04-06 14:21:35 +08:00
Harry Chen
d05c4cf09e Merge branch 'mipsel' of github.com:oscourse-tsinghua/rcore_plus into mipsel 2019-04-06 14:17:24 +08:00
Harry Chen
b75e388aa1 Fix backtrace for mipsel 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-06 14:15:55 +08:00
Jiajie Chen
6335597897 Add netlink socket skeleton 2019-04-06 13:33:17 +08:00
Yuhao Zhou
6038004576 Add page table lookup in pagefault. 2019-04-06 11:59:22 +08:00
Harry Chen
6cc607e0c8 Make aarch64 and mipsel use img instead of qcow 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-06 11:20:50 +08:00
Yuhao Zhou
9a9e8048cb Move text base to higher location to avoid colliding with qemu BIOS 2019-04-06 03:22:26 +08:00
Yuhao Zhou
fb08410cb5 Fix paging bug. 2019-04-06 02:46:40 +08:00
Harry Chen
6e2947ac56 Fix uart address definition on thinpad 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-06 02:43:00 +08:00
Harry Chen
96caa80914 Extract some board-specfic constants 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-06 02:20:49 +08:00
Yuhao Zhou
26a5847a0a Merge branch 'mipsel' of github.com:oscourse-tsinghua/rcore_plus into mipsel 2019-04-06 02:11:21 +08:00
Yuhao Zhou
cbb4431231 Fix memory size. 2019-04-06 02:10:30 +08:00
Harry Chen
a040d5c9d6 Merge branch 'mipsel' of github.com:oscourse-tsinghua/rcore_plus into mipsel 2019-04-06 01:57:44 +08:00
Harry Chen
c3e94d38ae Fix early uart on malta, now malta board can print things! 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-06 01:57:23 +08:00
Yuhao Zhou
e5eeccffaf Merge. 2019-04-06 01:04:16 +08:00
Yuhao Zhou
610fd5b3db Fix MIPS registers access in backtrace.rs. 2019-04-06 01:01:10 +08:00
Harry Chen
06f7b1643d Fix makefile options for mipsel 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-06 00:58:32 +08:00
Harry Chen
f5227e28d3 Fix register naming in backtrace 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-06 00:55:08 +08:00
Yuhao Zhou
7c20ebf6e0 Remove dtb.S. 2019-04-06 00:48:24 +08:00
Yuhao Zhou
c9980f1efb Fix context switch. 2019-04-06 00:45:41 +08:00
Harry Chen
8e01458ae0 Update user app repo 
Signed-off-by: Harry Chen <i@harrychen.xyz>
 2019-04-06 00:38:36 +08:00