70 Commits

Author	SHA1	Message	Date
WangRunji	5ce7d0a9c0	use user shell by default. fix kernel shell removing user thread.	2018-11-16 01:22:59 +08:00
WangRunji	16fb733497	Blocking getchar	2018-11-05 22:55:59 +08:00
WangRunji	e5a196c00f	Fix processor. Disable interrupt on switching.	2018-11-02 10:25:41 +08:00
WangRunji	5852881611	unwrap -> expect	2018-11-01 23:45:48 +08:00
WangRunji	b7d6b2989d	Fix bugs. Pass test 'spin' ... - Fix ACK IRQ on x86. - Add process exit handler.	2018-11-01 21:10:19 +08:00
WangRunji	74facd8e87	Use Vec to replace array in ProcessManager.	2018-11-01 00:16:32 +08:00
WangRunji	7229b49eb8	Use rust-lld for RV32. Remove riscv git submodule.	2018-10-30 13:30:20 +08:00
WangRunji	72dc3f62ad	Remove kernel stack from MemorySet.	2018-10-27 15:17:15 +08:00
WangRunji	438e290b6d	Fix PageTable::get_entry -> Option.	2018-10-26 23:43:12 +08:00
WangRunji	0680023e35	Recover wait/sleep	2018-10-26 00:49:19 +08:00
WangRunji	c734f79699	Drop context when process exit. Remove util mod.	2018-10-25 01:04:31 +08:00
WangRunji	85a1dca684	Use weak linkage to provide dependencies for process::thread.	2018-10-24 21:32:23 +08:00
WangRunji	80b161db98	Recover set_priority and fork	2018-10-24 21:29:41 +08:00
WangRunji	5db908b1c5	Separate ProcessManager to a mod.	2018-10-24 00:38:22 +08:00
WangRunji	f7eb09e856	Multicore processing WORKS! Basically ... ... - Rewrite processor.rs Refactor to `Processor` & `ProcessManager` - Use Box<dyn> instead of generic. - Wait/sleep/wakeup is not supported yet. I'm considering to implement them with WaitQueue.	2018-10-24 00:28:29 +08:00
WangRunji	5bc392f388	Enable RV32 IPI.	2018-10-21 21:47:17 +08:00
WangRunji	fc2fd18c36	Add docs for thread::spawn()	2018-09-22 17:32:16 +08:00
WangRunji	7dd9494389	Add Scheduler.move_to_head(pid) to replace Processor.next ... Rename `set_reschedule` to `yield_now`	2018-09-22 15:54:22 +08:00
WangRunji	501ce6c4be	Fix memory crate test compile.	2018-09-21 16:00:48 +08:00
WangRunji	cd1bd55729	Update README, travis, riscv crate.	2018-09-19 20:58:00 +08:00
WangRunji	924c061d64	Merge branch 'x86-boot' ... # Conflicts: # crate/riscv # kernel/Makefile	2018-09-19 20:18:14 +08:00
dzy	5a0ce1e464	Refactored RISC-V page table identity mapping into a function.	2018-09-14 21:44:25 +08:00
dzy	906019f7c6	Add little notes for BitAllocator	2018-09-07 20:53:37 +08:00
WangRunji	caeff9ad97	Update packages and fit for new Rust nightly	2018-09-04 13:19:23 +08:00
WangRunji	b88648ff44	Fit for newest Rust nightly. x86_64 ok, riscv32 broken.	2018-08-04 16:20:25 +08:00
WangRunji	a2111a928f	Move thread mod to ucore-process crate	2018-07-17 19:06:30 +08:00
WangRunji	776dc976c9	Fix for user	2018-07-17 12:07:21 +08:00
WangRunji	06b39ed521	Impl remove any for StrideScheduler	2018-07-17 11:01:51 +08:00
WangRunji	04b62ec79f	Use Vec instead of array in Scheduler	2018-07-17 02:13:42 +08:00
WangRunji	c8a9eaf3e6	Split process mod to extern crate	2018-07-17 01:56:28 +08:00
WangRunji	0c9679b710	Fix fork and syscall return value.	2018-07-15 01:07:25 +08:00
WangRunji	27daa6d491	Fix user trap	2018-07-15 00:45:53 +08:00
WangRunji	1ad3ed738e	Can run user program in RV32	2018-07-14 11:56:55 +08:00
WangRunji	89bcd5f660	Fix kernel thread	2018-07-13 01:45:48 +08:00
WangRunji	96d8af8034	Use CowExt for RV32	2018-07-12 19:44:13 +08:00
WangRunji	7d856fe009	Fix memory::cow LLVM error for RV32	2018-07-12 19:35:21 +08:00
WangRunji	5530549a54	Recover process thread sync mod for RV32. Pass compile.	2018-07-12 18:56:29 +08:00
WangRunji	7c7dbc9ded	Add CR3 to Context (x86_64)	2018-07-12 16:42:21 +08:00
WangRunji	95ab3a2f3b	Allocate kernel stack from heap, remove stack allocator, remove guard page.	2018-07-12 00:33:43 +08:00
WangRunji	81ff6f13e5	Fix recursive mapping, finish kernel remap.	2018-07-11 23:43:28 +08:00
WangRunji	d3ed84ba61	Fix compile	2018-07-11 00:53:40 +08:00
WangRunji	aecb85d5e7	Move MemorySet out to memory crate	2018-07-10 21:54:16 +08:00
WangRunji	5c14673fe0	Setup a simple page table, enable paging.	2018-07-10 17:37:38 +08:00
WangRunji	b26fee1990	Make more mods common for both x86_64 & riscv32.	2018-07-10 17:07:03 +08:00
WangRunji	ee242b44b2	Timer interrupt	2018-07-08 01:03:33 +08:00
WangRunji	aeb7fce0e6	SBI: Support RISCV64	2018-07-08 01:02:43 +08:00
WangRunji	02b94db859	Fix crate riscv version	2018-07-07 22:59:07 +08:00
WangRunji	bf2ad7c6a5	Change target arch to RISCV32IMA. Recover some dependencies.	2018-07-06 22:33:28 +08:00
WangRunji	a44231435f	Fork crate riscv as a submodule	2018-07-05 14:17:30 +08:00
WangRunji	ced765fb5b	New crate bbl, port sbi mod.	2018-07-04 22:04:59 +08:00