6 Commits

Author	SHA1	Message	Date
WangRunji	4914d22f44	Update doc & README	2018-07-12 22:46:17 +08:00
WangRunji	87b7ea523b	Experimental patch for core::sync::atomic on RISCV32I	2018-07-10 01:32:05 +08:00
WangRunji	a09be9cc40	Add doc for trap	2018-07-08 02:07:20 +08:00
WangRunji	aa22fcabde	Change target arch to RISCV32IMA. Recover some dependencies.	2018-07-06 23:02:10 +08:00
WangRunji	37564cb9fd	Change build target to riscv32ia_unknown_none	2018-07-06 01:24:35 +08:00
WangRunji	211aeff841	Add bbl as bootloader	2018-07-04 16:23:11 +08:00