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Author SHA1 Message Date
equation314
1140d32aaa add arch=aarch64 & board=raspi3 to Makefile 2018-10-26 11:22:26 +08:00
equation314
70abc9ec2e ignore .DS_Store 2018-10-26 11:22:22 +08:00
WangRunji
925a08f9ae Add OSLab/exp3 report 2018-10-26 02:32:48 +08:00
WangRunji
95ab9caba1 Add impl of atomic_fetch_* 2018-10-26 02:31:05 +08:00
WangRunji
0680023e35 Recover wait/sleep 2018-10-26 00:49:19 +08:00
WangRunji
c734f79699 Drop context when process exit. Remove util mod. 2018-10-25 01:04:31 +08:00
WangRunji
85a1dca684 Use weak linkage to provide dependencies for process::thread. 2018-10-24 21:32:23 +08:00
WangRunji
80b161db98 Recover set_priority and fork 2018-10-24 21:29:41 +08:00
WangRunji
5db908b1c5 Separate ProcessManager to a mod. 2018-10-24 00:38:22 +08:00
WangRunji
f7eb09e856 Multicore processing WORKS! Basically ... 
- Rewrite processor.rs
  Refactor to `Processor` & `ProcessManager`
- Use Box<dyn> instead of generic.
- Wait/sleep/wakeup is not supported yet.
  I'm considering to implement them with WaitQueue.
 2018-10-24 00:28:29 +08:00
WangRunji
6741ba399b Add arch::cpu::halt(). Halt when panic. 2018-10-24 00:23:40 +08:00
lcy1996
ec27ed8d2e add comment 2018-10-23 00:19:37 +08:00
lcy1996
5f34cc54d8 Merge branch 'OsTrain2018-g4' of github.com:oscourse-tsinghua/RustOS into lcy_issue1 2018-10-23 00:00:27 +08:00
lcy1996
63349ade19 Finish add more comment for kernel and finish set user memory swappable. 2018-10-23 00:00:09 +08:00
chenqiuhao
9474ad7220 update atomic function and workaround the LLVM compiling bug(maybe) 2018-10-22 18:40:21 +08:00
WangRunji
5bc392f388 Enable RV32 IPI. 2018-10-21 21:47:17 +08:00
WangRunji
ff18852c56 Reorganize docs. 2018-10-19 23:37:10 +08:00
WangRunji
1b4edf3bb2 Merge branch 'rv32-smp-porting' into dev 
# Conflicts:
#	kernel/Makefile
 2018-10-19 23:36:15 +08:00
WangRunji
72e92c07f9 Switch to RV64 GNU toolchain. Simplify compiler_rt. 2018-10-19 23:35:38 +08:00
WangRunji
f1771f8ef2 Finish x86 SMP startup. Support timer & IPI. 
- Remove smp, apic mod.
  Instead, use new bootloader & apic crate.
- Disable PIC & PIT.
  Instead, use IOAPIC & APIC Timer.
 2018-10-19 01:14:21 +08:00
maoyuchaxue
f27fd37d82 replaced spin::Mutex with sync::SpinLock, now spinlock works well. 2018-10-17 21:34:15 +08:00
maoyuchaxue
6df13c57ca Merge branch 'rv32-smp-porting' of https://github.com/char-fish-after-lunch/RustOS into rv32-smp-porting 2018-10-17 19:38:19 +08:00
maoyuchaxue
f7b7b1bcd6 added workaround for atomic ops 2018-10-17 19:37:53 +08:00
maoyuchaxue
cfda03a0f2 trying to add atomic implementations in rv32, but still buggy 2018-10-17 00:21:18 +08:00
lcy1996
0a81014007 Add page handler for swap in/out in riscv32's pagefault 2018-10-16 21:51:17 +08:00
maoyuchaxue
a34783c277 a late proposal.pptx 2018-10-16 18:05:16 +08:00
maoyuchaxue
d55eae7122 a late proposal.md 2018-10-16 17:42:50 +08:00
maoyuchaxue
49cd04dce3 added rv32 smp booting, with slight modification to bbl 2018-10-14 22:28:01 +08:00
maoyuchaxue
6cf0d6db23 fixed setting in riscv-pk to enable rv32ia, added smp option in Makefile 2018-10-14 13:50:59 +08:00
cfgbd
da74c628ec ignore eclipse files 2018-10-14 11:13:36 +08:00
lcy1996
0a7ec18701 Add page fault handler to riscv 32. 2018-10-11 21:30:35 +08:00
WangRunji
6cdf505f62 Add OSLab/exp2 report 2018-10-10 00:50:13 +08:00
Ben Pig Chu
f5acc273d7 Merge branch 'OsTrain2018-g4' of https://github.com/oscourse-tsinghua/RustOS into crate-memory-comment 2018-10-09 23:24:05 +08:00
Ben Pig Chu
7b69d01125 Merge branch 'OsTrain2018-g4' of https://github.com/oscourse-tsinghua/RustOS into crate-memory-comment 2018-10-09 23:21:00 +08:00
lcy1996
c9ed233428 Modified Proposal 2018-10-09 23:20:11 +08:00
Ben Pig Chu
adf474b78f file system planning 2018-10-09 23:19:13 +08:00
chenqiuhao1997
dc95f9c605
Update proposal.md 2018-10-09 21:43:44 +08:00
chenqiuhao1997
f64b8c7f6a
Update proposal.md 2018-10-09 21:42:57 +08:00
Ben Pig Chu
fc727b9618 Merge branch 'OsTrain2018-g4' of https://github.com/oscourse-tsinghua/RustOS into crate-memory-comment 2018-10-09 21:42:13 +08:00
Ben Pig Chu
4a17ce8f16 comments of crate/memory 2018-10-09 21:39:34 +08:00
lcy1996
683355180c Modified Proposal 2018-10-09 21:21:38 +08:00
lcy1996
25db09bd59 Modified Proposal 2018-10-09 21:19:55 +08:00
chenqiuhao
24d0de8c42 update report 2018-10-09 21:19:32 +08:00
lcy1996
5a1cc4178d Modified proposal 2018-10-09 21:17:14 +08:00
chenqiuhao
0ba43762ff update report 2018-10-09 21:17:00 +08:00
lcy1996
96cdf37b15 Add some comment for paging and add proposal doc 2018-10-09 21:11:14 +08:00
lcy1996
cef2d792be Add part of comments for riscv32 module 2018-10-08 01:47:13 +08:00
lcy1996
2157e4bbcf Add comment for interrutp and trap code 2018-10-06 01:45:56 +08:00
lcy1996
91455d163d Finish comment riscv context. 2018-10-05 23:39:28 +08:00
lcy1996
65df061ec6 Update expr1 report. 2018-10-05 22:16:07 +08:00