Add Rocket Chip platform in README

README.md

@@ -8,7 +8,7 @@ Going to be the next generation teaching operating system.
 
 Supported architectures: x86_64, RISCV32/64, AArch64, MIPS32
 
-Tested boards: QEMU, HiFive Unleashed, x86_64 PC (i5/i7), Raspberry Pi 3B+
+Tested boards: QEMU, HiFive Unleashed, x86_64 PC (i5/i7), Raspberry Pi 3B+, Kendryte K210 and FPGA running Rocket Chip
 
 ![demo](./docs/2_OSLab/os2atc/demo.png)
 

crate/memory/src/memory_set/mod.rs

@@ -58,7 +58,8 @@ impl MemoryArea {
     fn check_read_array<S>(&self, ptr: *const S, count: usize) -> bool {
         // page align
         ptr as usize >= Page::of_addr(self.start_addr).start_address()
-            && unsafe { ptr.add(count) as usize } < Page::of_addr(self.end_addr + PAGE_SIZE - 1).start_address()
+            && unsafe { ptr.add(count) as usize }
+                < Page::of_addr(self.end_addr + PAGE_SIZE - 1).start_address()
     }
     /// Check the array is within the writable memory
     fn check_write_array<S>(&self, ptr: *mut S, count: usize) -> bool {

kernel/src/arch/riscv32/boot/linker64.ld

@@ -0,0 +1,49 @@
+/* Copy from bbl-ucore : https://ring00.github.io/bbl-ucore      */
+
+/* Simple linker script for the ucore kernel.
+   See the GNU ld 'info' manual ("info ld") to learn the syntax. */
+
+OUTPUT_ARCH(riscv)
+ENTRY(_start)
+
+BASE_ADDRESS = 0xffffffffc0200000;
+
+SECTIONS
+{
+    /* Load the kernel at this address: "." means the current address */
+    . = BASE_ADDRESS;
+    start = .;
+
+    .text : {
+        stext = .;
+        *(.text.entry)
+        *(.text .text.*)
+        . = ALIGN(4K);
+        etext = .;
+    }
+
+    .rodata : {
+        srodata = .;
+        *(.rodata .rodata.*)
+        . = ALIGN(4K);
+        erodata = .;
+    }
+
+    .data : {
+        sdata = .;
+        *(.data .data.*)
+        edata = .;
+    }
+
+    .stack : {
+        *(.bss.stack)
+    }
+
+    .bss : {
+        sbss = .;
+        *(.bss .bss.*)
+        ebss = .;
+    }
+
+    PROVIDE(end = .);
+}