From ba4a24ba3be63cb1bacfa2f4e7bb7b4a501f8774 Mon Sep 17 00:00:00 2001 From: WangRunji Date: Fri, 2 Nov 2018 16:09:39 +0800 Subject: [PATCH] Fix RV32 multi-core: Setup page table for other cores. --- kernel/src/arch/riscv32/memory.rs | 17 ++++++++++++++--- kernel/src/arch/riscv32/mod.rs | 1 + 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/kernel/src/arch/riscv32/memory.rs b/kernel/src/arch/riscv32/memory.rs index 7e0c08cc..bd3be704 100644 --- a/kernel/src/arch/riscv32/memory.rs +++ b/kernel/src/arch/riscv32/memory.rs @@ -1,4 +1,4 @@ -use core::slice; +use core::{slice, mem}; use memory::{active_table, FRAME_ALLOCATOR, init_heap, MemoryArea, MemoryAttr, MemorySet}; use super::riscv::{addr::*, register::sstatus}; use ucore_memory::PAGE_SIZE; @@ -16,6 +16,13 @@ pub fn init() { remap_the_kernel(); } +pub fn init_other() { + unsafe { + sstatus::set_sum(); // Allow user memory access + asm!("csrw 0x180, $0; sfence.vma" :: "r"(SATP) :: "volatile"); + } +} + fn init_frame_allocator() { use bit_allocator::BitAlloc; use core::ops::Range; @@ -42,11 +49,15 @@ fn remap_the_kernel() { ms.push(MemoryArea::new_identity(srodata as usize, erodata as usize, MemoryAttr::default().readonly(), "rodata")); ms.push(MemoryArea::new_identity(sbss as usize, ebss as usize, MemoryAttr::default(), "bss")); unsafe { ms.activate(); } - use core::mem::forget; - forget(ms); + unsafe { SATP = ms.token(); } + mem::forget(ms); info!("kernel remap end"); } +// First core stores its SATP here. +// Other cores load it later. +static mut SATP: usize = 0; + // Symbols provided by linker script extern { fn stext(); diff --git a/kernel/src/arch/riscv32/mod.rs b/kernel/src/arch/riscv32/mod.rs index de43a259..963faeae 100644 --- a/kernel/src/arch/riscv32/mod.rs +++ b/kernel/src/arch/riscv32/mod.rs @@ -35,6 +35,7 @@ pub extern fn rust_main(hartid: usize, dtb: usize, hart_mask: usize) -> ! { fn others_main() -> ! { interrupt::init(); + memory::init_other(); timer::init(); ::kmain(); }