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Fixed RISC-V tlb not flushed during context switch

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Added a missing SFENCE.VMA
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Liu Xiaoyi 2020-06-08 16:39:46 +08:00 committed by GitHub
parent 2a7d48b528
commit b41147f436
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1 changed files with 1 additions and 0 deletions
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kernel/src/arch/riscv/context.rs
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@ -185,6 +185,7 @@ impl Context {
Load sp, 0(a1)
Load s11, 1*XLENB(sp)
csrw satp, s11
sfence.vma
Load ra, 0*XLENB(sp)
Load s0, 2*XLENB(sp)
Load s1, 3*XLENB(sp)