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Fix many bugs.

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* timer counter overflow
* clear TLB when switching context
* fix cp0.ebase access (sel = 1)
* clear TLB when editing page table
This commit is contained in:
Yuhao Zhou 2019-04-08 22:35:02 +08:00
parent 2baf15acac
commit 9078190e28
5 changed files with 19 additions and 14 deletions
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8
kernel/src/arch/mipsel/boot/context.S
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@ -28,13 +28,13 @@ switch_context:
// save page table address // save page table address
la s0, _root_page_table_ptr la s0, _root_page_table_ptr
lw AT, 0(s0) lw s1, 0(s0)
sw AT, 4(sp) sw s1, 4(sp)
// restore to's registers // restore to's registers
lw sp, 0(a1) lw sp, 0(a1)
lw AT, 4(sp) lw s1, 4(sp)
sw AT, 0(s0) sw s1, 0(s0)
// restore kstack ptr // restore kstack ptr
// la s0, _cur_kstack_ptr // la s0, _cur_kstack_ptr

4
kernel/src/arch/mipsel/boot/entry.S
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@ -17,9 +17,9 @@ _start:
# set ebase # set ebase
la t0, trap_entry la t0, trap_entry
mfc0 t1, $15 # C0_EBASE mfc0 t1, $15, 1 # C0_EBASE
or t1, t1, t0 or t1, t1, t0
mtc0 t1, $15 mtc0 t1, $15, 1
# exit bootstrap mode # exit bootstrap mode
mfc0 t0, $12 # C0_STATUS mfc0 t0, $12 # C0_STATUS

7
kernel/src/arch/mipsel/context.rs
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@ -118,7 +118,7 @@ impl InitStack {
} }
} }
extern { extern "C" {
fn trap_return(); fn trap_return();
} }
@ -161,8 +161,7 @@ impl Context {
fn switch_context(src: *mut Context, dst: *mut Context); fn switch_context(src: *mut Context, dst: *mut Context);
} }
info!("Switch to {:x}", target.sp); tlb::clear_all_tlb();
switch_context(self as *mut Context, target as *mut Context); switch_context(self as *mut Context, target as *mut Context);
} }
@ -230,7 +229,7 @@ impl Context {
let mut tf = tf.clone(); let mut tf = tf.clone();
tf.sp = ustack_top; // sp tf.sp = ustack_top; // sp
tf.v1 = tls; tf.v1 = tls;
tf.a0 = 0; // return value tf.v0 = 0; // return value
tf tf
}, },
}.push_at(kstack_top) }.push_at(kstack_top)

9
kernel/src/arch/mipsel/paging.rs
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@ -51,6 +51,7 @@ extern "C" {
pub fn set_root_page_table_ptr(ptr : usize) { pub fn set_root_page_table_ptr(ptr : usize) {
unsafe { unsafe {
clear_all_tlb();
*(_root_page_table_ptr as *mut usize) = ptr; *(_root_page_table_ptr as *mut usize) = ptr;
} }
} }
@ -157,13 +158,19 @@ impl InactivePageTable for InactivePageTable0 {
self.token() as *mut MIPSPageTable self.token() as *mut MIPSPageTable
}; };
unsafe { clear_all_tlb(); }
let mut active = unsafe { let mut active = unsafe {
ActivePageTable( ActivePageTable(
TwoLevelPageTable::new(&mut *pt), TwoLevelPageTable::new(&mut *pt),
::core::mem::uninitialized() ::core::mem::uninitialized()
) )
}; };
f(&mut active)
let ret = f(&mut active);
unsafe { clear_all_tlb(); }
ret
} }
} }

5
kernel/src/arch/mipsel/timer.rs
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@ -19,7 +19,6 @@ pub fn init() {
pub fn set_next() { pub fn set_next() {
// 100Hz @ QEMU // 100Hz @ QEMU
let timebase = 250000; let timebase = 250000;
cp0::compare::write_u32( cp0::count::write_u32(0);
cp0::count::read_u32() + timebase cp0::compare::write_u32(timebase);
);
} }