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Setup x87 FPU control word correctly
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e32597ac82
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@ -43,10 +43,13 @@ pub fn init() {
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// enable FPU, the manual Volume 3 Chapter 13
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// enable FPU, the manual Volume 3 Chapter 13
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unsafe {
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unsafe {
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Cr4::update(|cr4| {
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Cr4::update(|cr4| {
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// enable fxsave/fxrstor
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cr4.insert(Cr4Flags::OSFXSR);
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cr4.insert(Cr4Flags::OSFXSR);
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// sse
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cr4.insert(Cr4Flags::OSXMMEXCPT_ENABLE);
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cr4.insert(Cr4Flags::OSXMMEXCPT_ENABLE);
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});
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});
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Cr0::update(|cr0| {
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Cr0::update(|cr0| {
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// enable fpu
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cr0.remove(Cr0Flags::EMULATE_COPROCESSOR);
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cr0.remove(Cr0Flags::EMULATE_COPROCESSOR);
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cr0.insert(Cr0Flags::MONITOR_COPROCESSOR);
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cr0.insert(Cr0Flags::MONITOR_COPROCESSOR);
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});
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});
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@ -5,7 +5,10 @@
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#[derive(Debug, Copy, Clone, Default)]
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#[derive(Debug, Copy, Clone, Default)]
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pub struct FpState {
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pub struct FpState {
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// 0
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// 0
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word1: u64,
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fcw: u16,
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fsw: u16,
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ftw: u16,
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fop: u16,
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word2: u64,
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word2: u64,
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// 16
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// 16
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word3: u64,
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word3: u64,
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@ -23,8 +26,11 @@ impl FpState {
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pub fn new() -> Self {
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pub fn new() -> Self {
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assert!(core::mem::size_of::<Self>() == 512);
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assert!(core::mem::size_of::<Self>() == 512);
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Self {
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Self {
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// default value
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// default values
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// intel manual 11.6.4 Initialization of SSE/SSE2 Extensions
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mxcsr: 0x1f80,
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mxcsr: 0x1f80,
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// intel manual 8.1.5 x87 FPU Control Word
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fcw: 0x03f7,
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..Self::default()
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..Self::default()
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}
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}
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}
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}
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