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https://github.com/rcore-os/rCore.git
synced 2025-01-19 01:07:05 +04:00
Add missing functions for riscv
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@ -75,6 +75,7 @@ compression = { version = "0.1.4", default-features = false, features = ["gzip"]
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num = { version = "0.2.1", default-features = false }
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num-traits = { version = "0.2.11", default-features = false }
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num-derive = "0.3"
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pc-keyboard = "0.5"
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[target.'cfg(target_arch = "x86_64")'.dependencies]
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rboot = { path = "../rboot", default-features = false }
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@ -82,7 +83,6 @@ apic = { git = "https://github.com/rcore-os/apic-rs" }
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x86_64 = "0.7"
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raw-cpuid = "7.0"
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uart_16550 = "0.2"
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pc-keyboard = "0.5"
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acpi = "0.4"
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aml = "0.4"
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@ -52,6 +52,11 @@ impl TrapFrame {
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tf.sstatus.set_spp(sstatus::SPP::User);
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tf
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}
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pub fn get_sp(&self) -> usize {
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// sp is x2
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self.x[2]
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}
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}
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use core::fmt::{Debug, Error, Formatter};
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@ -112,7 +112,7 @@ fn timer() {
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crate::trap::timer();
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}
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fn syscall(tf: &mut TrapFrame) {
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pub fn syscall(tf: &mut TrapFrame) {
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tf.sepc += 4; // Must before syscall, because of fork.
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let ret = crate::syscall::syscall(
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tf.x[17],
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@ -17,6 +17,7 @@ pub mod memory;
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pub mod paging;
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pub mod rand;
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mod sbi;
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pub mod signal;
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pub mod syscall;
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pub mod timer;
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@ -119,3 +120,17 @@ global_asm!(include_str!("boot/entry64.asm"));
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#[cfg(feature = "board_k210")]
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global_asm!(include_str!("boot/entry_k210.asm"));
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global_asm!(include_str!("boot/trap.asm"));
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pub fn get_sp() -> usize {
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let sp: usize;
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unsafe {
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asm!("mv $0, sp" : "=r"(sp));
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}
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sp
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}
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pub fn set_sp(sp: usize) {
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unsafe {
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asm!("mv sp, $0" :: "r" (sp) : "memory");
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}
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}
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40
kernel/src/arch/riscv/signal.rs
Normal file
40
kernel/src/arch/riscv/signal.rs
Normal file
@ -0,0 +1,40 @@
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use crate::arch::interrupt::TrapFrame;
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#[repr(C)]
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#[derive(Clone, Debug)]
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pub struct MachineContext {
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pub r8: usize,
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pub r9: usize,
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pub r10: usize,
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pub r11: usize,
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pub r12: usize,
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pub r13: usize,
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pub r14: usize,
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pub r15: usize,
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pub rdi: usize,
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pub rsi: usize,
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pub rbp: usize,
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pub rbx: usize,
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pub rdx: usize,
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pub rax: usize,
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pub rcx: usize,
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pub rsp: usize,
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pub rip: usize,
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pub eflags: usize,
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pub cs: u16,
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pub gs: u16,
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pub fs: u16,
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pub _pad: u16,
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pub err: usize,
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pub trapno: usize,
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pub oldmask: usize,
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pub cr2: usize,
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pub fpstate: usize,
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pub _reserved1: [usize; 8],
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}
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impl MachineContext {
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pub fn from_tf(tf: &TrapFrame) -> Self {
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todo!()
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}
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}
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@ -12,6 +12,8 @@ pub const INFORM_PER_MSEC: usize = 50;
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#[cfg(target_arch = "x86_64")]
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pub const ARCH: &'static str = "x86_64";
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#[cfg(target_arch = "riscv64")]
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pub const ARCH: &'static str = "riscv64";
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lazy_static! {
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pub static ref SMP_CORES: usize = {
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@ -25,6 +25,7 @@ pub use self::mem::*;
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pub use self::misc::*;
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pub use self::net::*;
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pub use self::proc::*;
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#[cfg(target_arch = "x86_64")]
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pub use self::signal::*;
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pub use self::time::*;
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@ -36,6 +37,7 @@ mod mem;
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mod misc;
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mod net;
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mod proc;
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#[cfg(target_arch = "x86_64")]
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mod signal;
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mod time;
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@ -210,22 +212,27 @@ impl Syscall<'_> {
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SYS_MADVISE => self.unimplemented("madvise", Ok(0)),
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// signal
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#[cfg(target_arch = "x86_64")]
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SYS_RT_SIGACTION => self.sys_rt_sigaction(
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args[0],
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args[1] as *const SignalAction,
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args[2] as *mut SignalAction,
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args[3],
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),
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#[cfg(target_arch = "x86_64")]
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SYS_RT_SIGRETURN => self.sys_rt_sigreturn(),
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#[cfg(target_arch = "x86_64")]
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SYS_RT_SIGPROCMASK => self.sys_rt_sigprocmask(
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args[0],
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args[1] as *const Sigset,
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args[2] as *mut Sigset,
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args[3],
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),
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#[cfg(target_arch = "x86_64")]
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SYS_SIGALTSTACK => {
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self.sys_sigaltstack(args[0] as *const SignalStack, args[1] as *mut SignalStack)
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}
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#[cfg(target_arch = "x86_64")]
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SYS_KILL => self.sys_kill(args[0] as isize, args[1]),
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// schedule
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@ -300,6 +307,7 @@ impl Syscall<'_> {
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args[2] as i32,
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args[3] as *const TimeSpec,
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),
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#[cfg(target_arch = "x86_64")]
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SYS_TKILL => self.sys_tkill(args[0], args[1]),
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// time
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