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mirror of https://github.com/rcore-os/rCore.git synced 2025-01-19 01:07:05 +04:00

Add missing functions for riscv

This commit is contained in:
Jiajie Chen 2020-06-12 09:10:25 +08:00
parent 8afcade90a
commit 5b01f1b6ad
7 changed files with 72 additions and 2 deletions

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@ -75,6 +75,7 @@ compression = { version = "0.1.4", default-features = false, features = ["gzip"]
num = { version = "0.2.1", default-features = false }
num-traits = { version = "0.2.11", default-features = false }
num-derive = "0.3"
pc-keyboard = "0.5"
[target.'cfg(target_arch = "x86_64")'.dependencies]
rboot = { path = "../rboot", default-features = false }
@ -82,7 +83,6 @@ apic = { git = "https://github.com/rcore-os/apic-rs" }
x86_64 = "0.7"
raw-cpuid = "7.0"
uart_16550 = "0.2"
pc-keyboard = "0.5"
acpi = "0.4"
aml = "0.4"

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@ -52,6 +52,11 @@ impl TrapFrame {
tf.sstatus.set_spp(sstatus::SPP::User);
tf
}
pub fn get_sp(&self) -> usize {
// sp is x2
self.x[2]
}
}
use core::fmt::{Debug, Error, Formatter};

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@ -112,7 +112,7 @@ fn timer() {
crate::trap::timer();
}
fn syscall(tf: &mut TrapFrame) {
pub fn syscall(tf: &mut TrapFrame) {
tf.sepc += 4; // Must before syscall, because of fork.
let ret = crate::syscall::syscall(
tf.x[17],

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@ -17,6 +17,7 @@ pub mod memory;
pub mod paging;
pub mod rand;
mod sbi;
pub mod signal;
pub mod syscall;
pub mod timer;
@ -119,3 +120,17 @@ global_asm!(include_str!("boot/entry64.asm"));
#[cfg(feature = "board_k210")]
global_asm!(include_str!("boot/entry_k210.asm"));
global_asm!(include_str!("boot/trap.asm"));
pub fn get_sp() -> usize {
let sp: usize;
unsafe {
asm!("mv $0, sp" : "=r"(sp));
}
sp
}
pub fn set_sp(sp: usize) {
unsafe {
asm!("mv sp, $0" :: "r" (sp) : "memory");
}
}

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@ -0,0 +1,40 @@
use crate::arch::interrupt::TrapFrame;
#[repr(C)]
#[derive(Clone, Debug)]
pub struct MachineContext {
pub r8: usize,
pub r9: usize,
pub r10: usize,
pub r11: usize,
pub r12: usize,
pub r13: usize,
pub r14: usize,
pub r15: usize,
pub rdi: usize,
pub rsi: usize,
pub rbp: usize,
pub rbx: usize,
pub rdx: usize,
pub rax: usize,
pub rcx: usize,
pub rsp: usize,
pub rip: usize,
pub eflags: usize,
pub cs: u16,
pub gs: u16,
pub fs: u16,
pub _pad: u16,
pub err: usize,
pub trapno: usize,
pub oldmask: usize,
pub cr2: usize,
pub fpstate: usize,
pub _reserved1: [usize; 8],
}
impl MachineContext {
pub fn from_tf(tf: &TrapFrame) -> Self {
todo!()
}
}

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@ -12,6 +12,8 @@ pub const INFORM_PER_MSEC: usize = 50;
#[cfg(target_arch = "x86_64")]
pub const ARCH: &'static str = "x86_64";
#[cfg(target_arch = "riscv64")]
pub const ARCH: &'static str = "riscv64";
lazy_static! {
pub static ref SMP_CORES: usize = {

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@ -25,6 +25,7 @@ pub use self::mem::*;
pub use self::misc::*;
pub use self::net::*;
pub use self::proc::*;
#[cfg(target_arch = "x86_64")]
pub use self::signal::*;
pub use self::time::*;
@ -36,6 +37,7 @@ mod mem;
mod misc;
mod net;
mod proc;
#[cfg(target_arch = "x86_64")]
mod signal;
mod time;
@ -210,22 +212,27 @@ impl Syscall<'_> {
SYS_MADVISE => self.unimplemented("madvise", Ok(0)),
// signal
#[cfg(target_arch = "x86_64")]
SYS_RT_SIGACTION => self.sys_rt_sigaction(
args[0],
args[1] as *const SignalAction,
args[2] as *mut SignalAction,
args[3],
),
#[cfg(target_arch = "x86_64")]
SYS_RT_SIGRETURN => self.sys_rt_sigreturn(),
#[cfg(target_arch = "x86_64")]
SYS_RT_SIGPROCMASK => self.sys_rt_sigprocmask(
args[0],
args[1] as *const Sigset,
args[2] as *mut Sigset,
args[3],
),
#[cfg(target_arch = "x86_64")]
SYS_SIGALTSTACK => {
self.sys_sigaltstack(args[0] as *const SignalStack, args[1] as *mut SignalStack)
}
#[cfg(target_arch = "x86_64")]
SYS_KILL => self.sys_kill(args[0] as isize, args[1]),
// schedule
@ -300,6 +307,7 @@ impl Syscall<'_> {
args[2] as i32,
args[3] as *const TimeSpec,
),
#[cfg(target_arch = "x86_64")]
SYS_TKILL => self.sys_tkill(args[0], args[1]),
// time