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Enable floating point in riscv

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This commit is contained in:
Jiajie Chen 2020-06-20 17:37:09 +08:00
parent b94b6aa09e
commit 4971713518
4 changed files with 14 additions and 5 deletions
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2
kernel/Cargo.lock generated
View File

@ -722,7 +722,7 @@ checksum = "3a385d94f3f62e60445a0adb9ff8d9621faa272234530d4c0f848ec98f88e316"
[[package]]
name = "trapframe"
version = "0.3.0"
source = "git+https://github.com/rcore-os/trapframe-rs?rev=7a3cd50#7a3cd505e9e0f5896b41772f156318c5d0e65c6f"
source = "git+https://github.com/rcore-os/trapframe-rs?rev=0efd4bd#0efd4bd5214971d635f5d3ee38884c987b876029"
dependencies = [
"log",
"raw-cpuid",

2
kernel/Cargo.toml
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@ -74,7 +74,7 @@ rcore-fs-devfs = { git = "https://github.com/rcore-os/rcore-fs", rev = "517af47"
rlibc = "1.0"
smoltcp = { git = "https://github.com/rcore-os/smoltcp", rev = "5bd87c7c", default-features = false, features = ["alloc", "log", "ethernet", "proto-ipv4", "proto-igmp", "socket-icmp", "socket-udp", "socket-tcp", "socket-raw"] }
spin = "0.5"
trapframe = { git = "https://github.com/rcore-os/trapframe-rs", rev = "7a3cd50" }
trapframe = { git = "https://github.com/rcore-os/trapframe-rs", rev = "0efd4bd" }
virtio-drivers = { git = "https://github.com/rcore-os/virtio-drivers", rev = "dfa70e14" }
volatile = "0.2"
woke = "0.0.2"

9
kernel/src/process/thread.rs
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@ -280,9 +280,14 @@ impl Thread {
context.set_ip(entry_addr);
context.set_sp(ustack_top);
#[cfg(target_arch = "x86_64")]
if true {
{
context.general.rflags = 0x3202;
}
#[cfg(target_arch = "riscv64")]
{
// SUM | FS | SPIE
context.sstatus = 1 << 18 | 1 << 14 | 1 << 13 | 1 << 5;
}
let thread = Thread {
tid: 0, // allocated below
@ -451,7 +456,7 @@ pub fn spawn(thread: Arc<Thread>) {
thread.vm.lock().handle_page_fault(addr as usize);
}
_ => {
warn!("unhandled trap {}", trap_num);
panic!("unhandled trap {} {:x?}", trap_num, cx);
}
}
thread.end_running(cx);

6
kernel/src/syscall/mod.rs
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@ -56,7 +56,7 @@ lazy_static! {
/// System call dispatcher
pub async fn handle_syscall(thread: &Arc<Thread>, context: &mut UserContext) -> bool {
let regs = &context.general;
let num = context.get_syscall_ret();
let num = context.get_syscall_num();
let args = context.get_syscall_args();
let mut syscall = Syscall {
thread,
@ -66,6 +66,10 @@ pub async fn handle_syscall(thread: &Arc<Thread>, context: &mut UserContext) ->
let ret = syscall.syscall(num, args).await;
let exit = syscall.exit;
context.set_syscall_ret(ret as usize);
#[cfg(target_arch = "riscv64")]
{
context.sepc = context.sepc + 4;
}
exit
}