mirror of
https://github.com/rcore-os/rCore.git
synced 2024-11-24 08:56:17 +04:00
Fix x86_64. Not elegant.
This commit is contained in:
WangRunji
parent
b61a2c9dd2
commit
3d6fcb8d8c
2
.gitignore
vendored
2
.gitignore
vendored
@ -1,3 +1,3 @@
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build
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target
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kernel/src/arch/x86_64/boot/vector.asm
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/kernel/src/arch/x86_64/interrupt/vector.asm
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@ -3,6 +3,9 @@ name = "ucore"
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version = "0.1.0"
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authors = ["Runji Wang <wangrunji0408@163.com>"]
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[lib]
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crate-type = ["staticlib", "rlib"]
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[features]
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use_apic = []
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link_user_program = []
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@ -27,7 +27,7 @@ user_bins := $(patsubst $(user_bin_path)/%.d, $(user_bin_path)/%, $(wildcard $(u
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user_obj := build/$(arch)/user.o
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SFSIMG := ../user/ucore32.img
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ifeq ($(arch), x86_64)
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qemu_opts := -cdrom $(iso) -smp 4 -serial mon:stdio -drive file=$(SFSIMG),media=disk,cache=writeback
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qemu_opts := -cdrom $(iso) -smp 4 -serial mon:stdio -drive file=$(SFSIMG),media=disk,cache=writeback -device isa-debug-exit
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endif
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ifeq ($(arch), riscv32)
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qemu_opts := -machine virt -kernel $(iso) -nographic
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@ -42,25 +42,8 @@ features := $(features) link_user_program
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assembly_object_files := $(assembly_object_files) $(user_obj)
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endif
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# Link user-riscv.img for RV32
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ifeq ($(arch), riscv32)
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riscv_user_img_obj := build/riscv32/user-riscv.o
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assembly_object_files := $(assembly_object_files) $(riscv_user_img_obj)
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endif
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ifdef travis
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test := 1
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features := $(features) qemu_auto_exit
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endif
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ifdef test
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features := $(features) test
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# enable shutdown inside the qemu
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qemu_opts := $(qemu_opts) -device isa-debug-exit
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endif
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ifdef int
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qemu_opts := $(qemu_opts) -d int
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ifdef d
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qemu_opts := $(qemu_opts) -d $(d)
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endif
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build_args := --target $(target).json --features "$(features)"
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@ -69,6 +52,10 @@ ifeq ($(mode), release)
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build_args := $(build_args) --release
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endif
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ifeq ($(arch), x86_64)
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build_args := $(build_args) --lib
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endif
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ifeq ($(OS),Windows_NT)
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uname := Win32
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@ -124,6 +111,7 @@ build/x86_64/os.iso: $(kernel) $(grub_cfg)
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@rm -r build/isofiles
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build/riscv32/os.iso: kernel
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@mkdir -p build/riscv32
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@cd ../riscv-pk && \
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mkdir -p build && \
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cd build && \
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@ -138,7 +126,7 @@ build/riscv32/os.iso: kernel
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$(kernel): kernel $(assembly_object_files) $(linker_script)
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@$(ld) -n --gc-sections -T $(linker_script) -o $(kernel) \
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$(assembly_object_files) $(rust_lib)
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$(assembly_object_files) target/x86_64-blog_os/$(mode)/libucore.a
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kernel:
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@CC=$(cc) cargo xbuild $(build_args)
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@ -148,18 +136,7 @@ build/x86_64/boot/%.o: $(boot_src)/%.asm
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@mkdir -p $(shell dirname $@)
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@nasm -felf64 $< -o $@
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build/riscv32/boot/%.o: $(boot_src)/%.asm
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@mkdir -p $(shell dirname $@)
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@$(as) -march=rv32i $< -o $@
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# make user.o from binary files
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$(user_obj): $(user_bins)
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@cd $(user_bin_path) && \
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$(ld) -o $(abspath $@) $(patsubst %, -b binary %, $(notdir $(user_bins)))
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$(riscv_user_img_obj): ../user/user-riscv.img
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@cd ../user && $(ld) -o $(abspath $@) -b binary $(notdir $<)
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# patch Rust core for RISCV32I atomic
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patch-core:
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@patch -p0 /rust/rust-riscv-rust-1.26.0-1-dev/src/libcore/sync/atomic.rs src/arch/riscv32/atomic.patch
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@ -15,11 +15,11 @@ fn main() {
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}
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fn gen_vector_asm() -> Result<()> {
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let mut f = File::create("src/arch/x86_64/boot/vector.asm").unwrap();
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let mut f = File::create("src/arch/x86_64/interrupt/vector.asm").unwrap();
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writeln!(f, "# generated by build.rs - do not edit")?;
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writeln!(f, "section .text")?;
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writeln!(f, "extern __alltraps")?;
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writeln!(f, ".section .text")?;
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writeln!(f, ".intel_syntax noprefix")?;
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for i in 0..256 {
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writeln!(f, "vector{}:", i)?;
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if !(i == 8 || (i >= 10 && i <= 14) || i == 17) {
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@ -29,11 +29,11 @@ fn gen_vector_asm() -> Result<()> {
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writeln!(f, "\tjmp __alltraps")?;
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}
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writeln!(f, "\nsection .rodata")?;
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writeln!(f, "global __vectors")?;
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writeln!(f, "\n.section .rodata")?;
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writeln!(f, ".global __vectors")?;
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writeln!(f, "__vectors:")?;
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for i in 0..256 {
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writeln!(f, "\tdq vector{}", i)?;
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writeln!(f, "\t.quad vector{}", i)?;
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}
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Ok(())
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}
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File diff suppressed because it is too large
Load Diff
@ -67,6 +67,9 @@
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use super::consts::*;
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use super::TrapFrame;
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global_asm!(include_str!("trap.asm"));
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global_asm!(include_str!("vector.asm"));
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#[no_mangle]
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pub extern fn rust_trap(tf: &mut TrapFrame) {
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trace!("Interrupt: {:#x}", tf.trap_num);
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@ -1,5 +1,7 @@
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section .text
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global __alltraps
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.section .text
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.global __alltraps
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.intel_syntax noprefix
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__alltraps:
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push rax
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push rcx
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@ -19,14 +21,12 @@ __alltraps:
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push r15
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mov rdi, rsp
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extern rust_trap
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call rust_trap
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global trap_ret
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.global trap_ret
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trap_ret:
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mov rdi, rsp
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extern set_return_rsp
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call set_return_rsp
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pop r15
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@ -46,7 +46,7 @@ trap_ret:
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pop rcx
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pop rax
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; pop trap_num, error_code
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# pop trap_num, error_code
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add rsp, 16
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iretq
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@ -40,12 +40,6 @@ extern crate volatile;
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extern crate x86_64;
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extern crate xmas_elf;
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// Export to asm
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pub use arch::interrupt::rust_trap;
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#[cfg(target_arch = "x86_64")]
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pub use arch::interrupt::set_return_rsp;
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#[cfg(target_arch = "x86_64")]
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pub use arch::other_main;
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use linked_list_allocator::LockedHeap;
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#[macro_use] // print!
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@ -66,7 +60,7 @@ mod console;
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#[allow(dead_code)]
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#[cfg(target_arch = "x86_64")]
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#[path = "arch/x86_64/mod.rs"]
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mod arch;
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pub mod arch;
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#[cfg(target_arch = "riscv32")]
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#[path = "arch/riscv32/mod.rs"]
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