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try to fix interrupt & deadlock on RV32

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This commit is contained in:
WangRunji 2018-11-26 16:58:45 +08:00
parent 46f0e85230
commit 2db453556d
3 changed files with 6 additions and 3 deletions
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4
crate/process/src/interrupt.rs
View File

@ -10,8 +10,8 @@ pub unsafe fn disable_and_store() -> usize {
#[cfg(target_arch = "riscv32")]
pub unsafe fn disable_and_store() -> usize {
let sstatus: usize;
asm!("csrrci $0, 0x100, 1" : "=r"(sstatus));
sstatus & 1
asm!("csrrci $0, 0x100, 2" : "=r"(sstatus));
sstatus & 2
}
#[inline(always)]

3
crate/process/src/processor.rs
View File

@ -92,7 +92,10 @@ impl Processor {
}
pub fn tick(&self) {
let flags = unsafe { interrupt::disable_and_store() };
let need_reschedule = self.manager().tick(self.pid());
unsafe { interrupt::restore(flags); }
if need_reschedule {
self.yield_now();
}

2
kernel/src/logging.rs
View File

@ -1,6 +1,6 @@
use core::fmt;
use log::{self, Level, LevelFilter, Log, Metadata, Record};
use spin::Mutex;
use crate::sync::SpinNoIrqLock as Mutex;
use lazy_static::lazy_static;
lazy_static! {