Merge branch 'dev' of github.com:rcore-os/rCore into dev

bootloader/Cargo.lock

@@ -2,8 +2,8 @@
 # It is not intended for manual editing.
 [[package]]
 name = "aarch64"
-version = "2.2.2"
+version = "2.5.0"
-source = "git+https://github.com/rcore-os/aarch64#14a08f4d285ae0ff515b03bff9f5e66eb68feaed"
+source = "git+https://github.com/rcore-os/aarch64#797c24f07f9d90542eb094530b6f63fe3ea7dded"
 dependencies = [
  "bit_field 0.9.0 (registry+https://github.com/rust-lang/crates.io-index)",
  "bitflags 1.0.4 (registry+https://github.com/rust-lang/crates.io-index)",
@@ -14,8 +14,8 @@ dependencies = [
 
 [[package]]
 name = "bcm2837"
-version = "0.1.0"
+version = "1.0.0"
-source = "git+https://github.com/rcore-os/bcm2837#446f0ea04deb5216ba5e08f10af36e5c1729e6fd"
+source = "git+https://github.com/rcore-os/bcm2837#b29a8db5504b7eaa6f8adf2c3ff916d1ffd15194"
 dependencies = [
  "volatile 0.2.6 (registry+https://github.com/rust-lang/crates.io-index)",
 ]
@@ -98,8 +98,8 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 name = "rcore-bootloader"
 version = "0.1.0"
 dependencies = [
- "aarch64 2.2.2 (git+https://github.com/rcore-os/aarch64)",
+ "aarch64 2.5.0 (git+https://github.com/rcore-os/aarch64)",
- "bcm2837 0.1.0 (git+https://github.com/rcore-os/bcm2837)",
+ "bcm2837 1.0.0 (git+https://github.com/rcore-os/bcm2837)",
  "cc 1.0.31 (registry+https://github.com/rust-lang/crates.io-index)",
  "fixedvec 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)",
  "xmas-elf 0.6.2 (registry+https://github.com/rust-lang/crates.io-index)",
@@ -205,8 +205,8 @@ version = "0.1.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 
 [metadata]
-"checksum aarch64 2.2.2 (git+https://github.com/rcore-os/aarch64)" = "<none>"
+"checksum aarch64 2.5.0 (git+https://github.com/rcore-os/aarch64)" = "<none>"
-"checksum bcm2837 0.1.0 (git+https://github.com/rcore-os/bcm2837)" = "<none>"
+"checksum bcm2837 1.0.0 (git+https://github.com/rcore-os/bcm2837)" = "<none>"
 "checksum bit_field 0.9.0 (registry+https://github.com/rust-lang/crates.io-index)" = "ed8765909f9009617974ab6b7d332625b320b33c326b1e9321382ef1999b5d56"
 "checksum bitflags 1.0.4 (registry+https://github.com/rust-lang/crates.io-index)" = "228047a76f468627ca71776ecdebd732a3423081fcf5125585bcd7c49886ce12"
 "checksum cc 1.0.31 (registry+https://github.com/rust-lang/crates.io-index)" = "c9ce8bb087aacff865633f0bd5aeaed910fe2fe55b55f4739527f2e023a2e53d"

bootloader/Cargo.toml

@@ -9,8 +9,8 @@ xmas-elf = "0.6.2"
 fixedvec = "0.2.3"
 
 [target.'cfg(target_arch = "aarch64")'.dependencies]
-aarch64 = { git = "https://github.com/rcore-os/aarch64" }
+aarch64 = { git = "https://github.com/rcore-os/aarch64", version = "2.5.0" }
-bcm2837 = { git = "https://github.com/rcore-os/bcm2837" }
+bcm2837 = { git = "https://github.com/rcore-os/bcm2837", version = "1.0.0" }
 
 [build-dependencies]
 cc = "1.0"

bootloader/src/main.rs

@@ -10,11 +10,7 @@ extern crate xmas_elf;
 use core::mem::transmute;
 use core::slice;
 use fixedvec::FixedVec;
-use xmas_elf::{
+use xmas_elf::{header, program::{self, ProgramHeader}, ElfFile};
-    header,
-    program::{ProgramHeader, ProgramHeader32, ProgramHeader64},
-    ElfFile,
-};
 
 #[cfg(target_arch = "aarch64")]
 #[path = "arch/aarch64/mod.rs"]
@@ -46,7 +42,7 @@ pub extern "C" fn boot_main() -> ! {
     let kernel_elf = ElfFile::new(kernel).unwrap();
     header::sanity_check(&kernel_elf).unwrap();
 
-    let mut preallocated_space = alloc_stack!([ProgramHeader64; 32]);
+    let mut preallocated_space = alloc_stack!([program::ProgramHeader64; 32]);
     let mut segments = FixedVec::new(&mut preallocated_space);
 
     for program_header in kernel_elf.program_iter() {
@@ -76,7 +72,7 @@ pub extern "C" fn boot_main() -> ! {
     let kernel_elf = ElfFile::new(kernel).unwrap();
     header::sanity_check(&kernel_elf).unwrap();
 
-    let mut preallocated_space = alloc_stack!([ProgramHeader32; 32]);
+    let mut preallocated_space = alloc_stack!([program::ProgramHeader32; 32]);
     let mut segments = FixedVec::new(&mut preallocated_space);
 
     for program_header in kernel_elf.program_iter() {

kernel/Cargo.lock

@@ -2,20 +2,8 @@
 # It is not intended for manual editing.
 [[package]]
 name = "aarch64"
-version = "2.2.2"
+version = "2.5.0"
-source = "git+https://github.com/equation314/aarch64#14a08f4d285ae0ff515b03bff9f5e66eb68feaed"
+source = "git+https://github.com/rcore-os/aarch64#797c24f07f9d90542eb094530b6f63fe3ea7dded"
-dependencies = [
- "bit_field 0.9.0 (registry+https://github.com/rust-lang/crates.io-index)",
- "bitflags 1.0.4 (registry+https://github.com/rust-lang/crates.io-index)",
- "register 0.2.1 (registry+https://github.com/rust-lang/crates.io-index)",
- "usize_conversions 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)",
- "ux 0.1.3 (registry+https://github.com/rust-lang/crates.io-index)",
-]
-
-[[package]]
-name = "aarch64"
-version = "2.2.2"
-source = "git+https://github.com/rcore-os/aarch64#14a08f4d285ae0ff515b03bff9f5e66eb68feaed"
 dependencies = [
  "bit_field 0.9.0 (registry+https://github.com/rust-lang/crates.io-index)",
  "bitflags 1.0.4 (registry+https://github.com/rust-lang/crates.io-index)",
@@ -52,10 +40,10 @@ dependencies = [
 
 [[package]]
 name = "bcm2837"
-version = "0.1.0"
+version = "1.0.0"
-source = "git+https://github.com/rcore-os/bcm2837#446f0ea04deb5216ba5e08f10af36e5c1729e6fd"
+source = "git+https://github.com/rcore-os/bcm2837#b29a8db5504b7eaa6f8adf2c3ff916d1ffd15194"
 dependencies = [
- "aarch64 2.2.2 (git+https://github.com/equation314/aarch64)",
+ "aarch64 2.5.0 (git+https://github.com/rcore-os/aarch64)",
  "volatile 0.2.6 (registry+https://github.com/rust-lang/crates.io-index)",
 ]
 
@@ -359,9 +347,9 @@ dependencies = [
 name = "rcore"
 version = "0.2.0"
 dependencies = [
- "aarch64 2.2.2 (git+https://github.com/rcore-os/aarch64)",
+ "aarch64 2.5.0 (git+https://github.com/rcore-os/aarch64)",
  "apic 0.1.0 (git+https://github.com/rcore-os/apic-rs)",
- "bcm2837 0.1.0 (git+https://github.com/rcore-os/bcm2837)",
+ "bcm2837 1.0.0 (git+https://github.com/rcore-os/bcm2837)",
  "bit_field 0.9.0 (registry+https://github.com/rust-lang/crates.io-index)",
  "bitflags 1.0.4 (registry+https://github.com/rust-lang/crates.io-index)",
  "bitmap-allocator 0.1.0 (git+https://github.com/rcore-os/bitmap-allocator)",
@@ -652,12 +640,11 @@ version = "0.1.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 
 [metadata]
-"checksum aarch64 2.2.2 (git+https://github.com/equation314/aarch64)" = "<none>"
+"checksum aarch64 2.5.0 (git+https://github.com/rcore-os/aarch64)" = "<none>"
-"checksum aarch64 2.2.2 (git+https://github.com/rcore-os/aarch64)" = "<none>"
 "checksum apic 0.1.0 (git+https://github.com/rcore-os/apic-rs)" = "<none>"
 "checksum array-init 0.0.4 (registry+https://github.com/rust-lang/crates.io-index)" = "23589ecb866b460d3a0f1278834750268c607e8e28a1b982c907219f3178cd72"
 "checksum bare-metal 0.2.4 (registry+https://github.com/rust-lang/crates.io-index)" = "a3caf393d93b2d453e80638d0674597020cef3382ada454faacd43d1a55a735a"
-"checksum bcm2837 0.1.0 (git+https://github.com/rcore-os/bcm2837)" = "<none>"
+"checksum bcm2837 1.0.0 (git+https://github.com/rcore-os/bcm2837)" = "<none>"
 "checksum bit_field 0.9.0 (registry+https://github.com/rust-lang/crates.io-index)" = "ed8765909f9009617974ab6b7d332625b320b33c326b1e9321382ef1999b5d56"
 "checksum bitflags 1.0.4 (registry+https://github.com/rust-lang/crates.io-index)" = "228047a76f468627ca71776ecdebd732a3423081fcf5125585bcd7c49886ce12"
 "checksum bitmap-allocator 0.1.0 (git+https://github.com/rcore-os/bitmap-allocator)" = "<none>"

kernel/Cargo.toml

@@ -81,8 +81,8 @@ pc-keyboard = "0.5"
 riscv = { git = "https://github.com/rcore-os/riscv", features = ["inline-asm"] }
 
 [target.'cfg(target_arch = "aarch64")'.dependencies]
-aarch64 = { git = "https://github.com/rcore-os/aarch64" }
+aarch64 = { git = "https://github.com/rcore-os/aarch64", version = "2.5.0" }
-bcm2837 = { git = "https://github.com/rcore-os/bcm2837", optional = true }
+bcm2837 = { git = "https://github.com/rcore-os/bcm2837", version = "1.0.0", optional = true }
 
 [target.'cfg(target_arch = "mips")'.dependencies]
 mips = "^0.2.0"

kernel/Makefile

@@ -75,10 +75,13 @@ board := raspi3
 need_bootloader := true
 endif
 
-# currently only mipsel architecture needs DTB linked to the kernel
+# currently only mipsel architecture and rocket-chip need DTB linked to the kernel
 ifeq ($(arch), mipsel)
 dtb := src/arch/$(arch)/board/$(board)/device.dtb
 endif
+ifeq ($(board), rocket_chip)
+dtb := src/arch/riscv32/board/$(board)/device.dtb
+endif
 
 # mipssim does not support SMP
 ifeq ($(board), mipssim)
@@ -330,6 +333,8 @@ ifeq ($(arch), x86_64)
 else ifeq ($(arch), $(filter $(arch), riscv32 riscv64))
 ifeq ($(board), k210)
 	@cp src/arch/riscv32/board/k210/linker.ld src/arch/riscv32/boot/linker64.ld
+else ifeq ($(board), rocket_chip)
+	@cp src/arch/riscv32/board/rocket_chip/linker.ld src/arch/riscv32/boot/linker64.ld
 else
 	@cp src/arch/riscv32/board/u540/linker.ld src/arch/riscv32/boot/linker64.ld
 endif

kernel/build.rs

@@ -16,7 +16,11 @@ fn main() {
             gen_vector_asm().unwrap();
         }
         "riscv32" => {}
-        "riscv64" => {}
+        "riscv64" => {
+            if board == "rocket_chip" {
+                gen_dtb_asm(&String::from("riscv32"), &board).unwrap();
+            }
+        }
         "mipsel" => {
             gen_dtb_asm(&arch, &board).unwrap();
         }

kernel/src/arch/aarch64/board/raspi3/mod.rs

@@ -78,5 +78,10 @@ pub fn probe_fb_info(width: u32, height: u32, depth: u32) -> FramebufferResult {
         ))?;
     }
 
-    Ok((info, fb::ColorConfig::BGRA8888, vaddr))
+    let color_config = match info.depth {
+        16 => ColorConfig::RGB565,
+        32 => ColorConfig::BGRA8888,
+        _ => Err(format!("unsupported color depth {}", info.depth))?,
+    };
+    Ok((info, color_config, vaddr))
 }

kernel/src/arch/aarch64/interrupt/mod.rs

@@ -11,12 +11,10 @@ pub use self::handler::*;
 
 /// Set the exception vector address
 pub fn init() {
-    unsafe {
+    extern "C" {
-        asm!(
+        fn __vectors();
-            "adr x0, __vectors;
-             msr vbar_el1, x0"
-        );
     }
+    VBAR_EL1.set(__vectors as u64);
 }
 
 /// Enable the interrupt (only IRQ).

kernel/src/arch/aarch64/paging.rs

@@ -12,7 +12,7 @@ use rcore_memory::paging::*;
 use crate::consts::{KERNEL_OFFSET, KERNEL_PML4, RECURSIVE_INDEX};
 use crate::memory::{active_table, alloc_frame, dealloc_frame};
 
-pub struct ActivePageTable(RecursivePageTable<'static>);
+pub struct ActivePageTable(RecursivePageTable);
 
 pub struct PageEntry(PageTableEntry);
 
@@ -34,8 +34,7 @@ impl PageTable for ActivePageTable {
     }
 
     fn unmap(&mut self, addr: usize) {
-        let (_frame, flush) = self.0.unmap(Page::of_addr(addr as u64)).unwrap();
+        self.0.unmap(Page::of_addr(addr as u64)).unwrap().1.flush();
-        flush.flush();
     }
 
     fn get_entry(&mut self, vaddr: usize) -> Option<&mut Entry> {
@@ -50,16 +49,9 @@ impl PageTableExt for ActivePageTable {
     const TEMP_PAGE_ADDR: usize = KERNEL_OFFSET | 0xcafeb000;
 }
 
-const ROOT_PAGE_TABLE: *mut Aarch64PageTable = (KERNEL_OFFSET
-    | (RECURSIVE_INDEX << 39)
-    | (RECURSIVE_INDEX << 30)
-    | (RECURSIVE_INDEX << 21)
-    | (RECURSIVE_INDEX << 12))
-    as *mut Aarch64PageTable;
-
 impl ActivePageTable {
     pub unsafe fn new() -> Self {
-        ActivePageTable(RecursivePageTable::new(&mut *(ROOT_PAGE_TABLE as *mut _)).unwrap())
+        ActivePageTable(RecursivePageTable::new(RECURSIVE_INDEX as u16))
     }
 }
 
@@ -198,12 +190,6 @@ pub struct InactivePageTable0 {
 impl InactivePageTable for InactivePageTable0 {
     type Active = ActivePageTable;
 
-    fn new() -> Self {
-        // When the new InactivePageTable is created for the user MemorySet, it's use ttbr1 as the
-        // TTBR. And the kernel TTBR ttbr0 will never changed, so we needn't call map_kernel()
-        Self::new_bare()
-    }
-
     fn new_bare() -> Self {
         let target = alloc_frame().expect("failed to allocate frame");
         let frame = Frame::of_addr(target as u64);
@@ -220,17 +206,8 @@ impl InactivePageTable for InactivePageTable0 {
     }
 
     fn map_kernel(&mut self) {
-        let table = unsafe { &mut *ROOT_PAGE_TABLE };
+        // When the new InactivePageTable is created for the user MemorySet, it's use ttbr0 as the
-        let e0 = table[KERNEL_PML4].clone();
+        // TTBR. And the kernel TTBR ttbr1 will never changed, so we needn't call map_kernel()
-        assert!(!e0.is_unused());
-
-        self.edit(|_| {
-            table[KERNEL_PML4].set_frame(
-                Frame::containing_address(e0.addr()),
-                EF::default(),
-                MairNormal::attr_value(),
-            );
-        });
     }
 
     fn token(&self) -> usize {
@@ -250,7 +227,11 @@ impl InactivePageTable for InactivePageTable0 {
     }
 
     fn edit<T>(&mut self, f: impl FnOnce(&mut Self::Active) -> T) -> T {
-        let target = ttbr_el1_read(1).start_address().as_u64() as usize;
+        let target = ttbr_el1_read(1);
+        if self.p4_frame == target {
+            return f(&mut active_table());
+        }
+        let target = target.start_address().as_u64() as usize;
         active_table().with_temporary_map(
             target,
             |active_table, p4_table: &mut Aarch64PageTable| {

kernel/src/arch/riscv32/board/rocket_chip/device.dts

@@ -0,0 +1,112 @@
+/dts-v1/;
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "freechips,rocketchip-unknown-dev";
+        model = "freechips,rocketchip-unknown";
+        L14: cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                L5: cpu@0 {
+                        clock-frequency = <0>;
+                        compatible = "sifive,rocket0", "riscv";
+                        d-cache-block-size = <64>;
+                        d-cache-sets = <64>;
+                        d-cache-size = <16384>;
+                        d-tlb-sets = <1>;
+                        d-tlb-size = <32>;
+                        device_type = "cpu";
+                        i-cache-block-size = <64>;
+                        i-cache-sets = <64>;
+                        i-cache-size = <16384>;
+                        i-tlb-sets = <1>;
+                        i-tlb-size = <32>;
+                        mmu-type = "riscv,sv39";
+                        next-level-cache = <&L6>;
+                        reg = <0>;
+                        riscv,isa = "rv64imafdc";
+                        status = "okay";
+                        timebase-frequency = <1000000>;
+                        tlb-split;
+                        L3: interrupt-controller {
+                                #interrupt-cells = <1>;
+                                compatible = "riscv,cpu-intc";
+                                interrupt-controller;
+                        };
+                };
+        };
+        L6: memory@80000000 {
+                device_type = "memory";
+                reg = <0x80000000 0x10000000>;
+        };
+        L13: soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "freechips,rocketchip-unknown-soc", "simple-bus";
+                ranges;
+                L11: blkdev-controller@10015000 {
+                        compatible = "ucbbar,blkdev";
+                        interrupt-parent = <&L0>;
+                        interrupts = <3>;
+                        reg = <0x10015000 0x1000>;
+                        reg-names = "control";
+                };
+                L1: clint@2000000 {
+                        compatible = "riscv,clint0";
+                        interrupts-extended = <&L3 3 &L3 7>;
+                        reg = <0x2000000 0x10000>;
+                        reg-names = "control";
+                };
+                L2: debug-controller@0 {
+                        compatible = "sifive,debug-013", "riscv,debug-013";
+                        interrupts-extended = <&L3 65535>;
+                        reg = <0x0 0x1000>;
+                        reg-names = "control";
+                };
+                L8: error-device@3000 {
+                        compatible = "sifive,error0";
+                        reg = <0x3000 0x1000>;
+                        reg-names = "mem";
+                };
+                L10: external-interrupts {
+                        interrupt-parent = <&L0>;
+                        interrupts = <1 2>;
+                };
+                L0: interrupt-controller@c000000 {
+                        #interrupt-cells = <1>;
+                        compatible = "riscv,plic0";
+                        interrupt-controller;
+                        interrupts-extended = <&L3 11 &L3 9>;
+                        reg = <0xc000000 0x4000000>;
+                        reg-names = "control";
+                        riscv,max-priority = <7>;
+                        riscv,ndev = <3>;
+                };
+                L7: mmio-port-axi4@60000000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        ranges = <0x60000000 0x60000000 0x20000000>;
+                        
+                        serial0: serial@60000000 {
+                                compatible = "xlnx,xps-uartlite-1.00.a";
+                                reg = <0x6000000 0x1000>;
+                                interrupt-parent = <&axi_intc>;
+                                interrupts = <1>;
+                        };
+
+                        axi_intc: axi_intc@61200000 {
+                                compatible = "xlnx,xps-intc-1.00.a";
+                                reg = <0x61200000 0x1000>;
+                                interrupt-parent = <&L10>;
+                                interrupts = <1>;
+                        };
+                };
+                L9: rom@10000 {
+                        compatible = "sifive,rom0";
+                        reg = <0x10000 0x10000>;
+                        reg-names = "mem";
+                };
+        };
+};

kernel/src/arch/riscv32/board/rocket_chip/linker.ld

@@ -0,0 +1,50 @@
+/* Copy from bbl-ucore : https://ring00.github.io/bbl-ucore      */
+
+/* Simple linker script for the ucore kernel.
+   See the GNU ld 'info' manual ("info ld") to learn the syntax. */
+
+OUTPUT_ARCH(riscv)
+ENTRY(_start)
+
+BASE_ADDRESS = 0xffffffffc0200000;
+
+SECTIONS
+{
+    /* Load the kernel at this address: "." means the current address */
+    . = BASE_ADDRESS;
+    start = .;
+
+    .text : {
+        stext = .;
+        *(.text.entry)
+        *(.text .text.*)
+        . = ALIGN(4K);
+        etext = .;
+    }
+
+    .rodata : {
+        srodata = .;
+        *(.rodata .rodata.*)
+        *(.dtb)
+        . = ALIGN(4K);
+        erodata = .;
+    }
+
+    .data : {
+        sdata = .;
+        *(.data .data.*)
+        edata = .;
+    }
+
+    .stack : {
+        *(.bss.stack)
+    }
+
+    .bss : {
+        sbss = .;
+        *(.bss .bss.*)
+        ebss = .;
+    }
+
+    PROVIDE(end = .);
+}

kernel/src/arch/riscv32/board/rocket_chip/mod.rs

@@ -0,0 +1,46 @@
+use super::consts::KERNEL_OFFSET;
+
+/// Mask all external interrupt except serial.
+pub unsafe fn init_external_interrupt() {
+    const HART0_S_MODE_INTERRUPT_ENABLES: *mut u64 = (KERNEL_OFFSET + 0x0C00_2080) as *mut u64;
+    HART0_S_MODE_INTERRUPT_ENABLES.write_volatile(0xf);
+
+    // mask interrupts first
+    const AXI_INTC_IER: *mut u32 = (KERNEL_OFFSET + 0x1900_0008) as *mut u32;
+    AXI_INTC_IER.write_volatile(0x0);
+
+    // acknowledge all interrupts
+    const AXI_INTC_IAR: *mut u32 = (KERNEL_OFFSET + 0x1900_000C) as *mut u32;
+    AXI_INTC_IAR.write_volatile(0xffffffff);
+
+    const AXI_INTC_MER: *mut u32 = (KERNEL_OFFSET + 0x1900_001C) as *mut u32;
+    // Hardware Interrupt enable | Enable irq output
+    AXI_INTC_MER.write_volatile(0b11);
+
+    // enable all interrupts
+    AXI_INTC_IER.write_volatile(0xffffffff);
+
+}
+
+/// Claim and complete external interrupt by reading and writing to
+/// PLIC Interrupt Claim/Complete Register.
+pub unsafe fn handle_external_interrupt() {
+    const HART0_S_MODE_INTERRUPT_CLAIM_COMPLETE: *mut u32 =
+        (KERNEL_OFFSET + 0x0C20_1004) as *mut u32;
+    // claim
+    let source = HART0_S_MODE_INTERRUPT_CLAIM_COMPLETE.read_volatile();
+    // complete
+    HART0_S_MODE_INTERRUPT_CLAIM_COMPLETE.write_volatile(source);
+
+    // acknowledge all interrupts
+    const AXI_INTC_IAR: *mut u32 = (KERNEL_OFFSET + 0x1900_000C) as *mut u32;
+    AXI_INTC_IAR.write_volatile(0xffffffff);
+}
+
+pub unsafe fn enable_serial_interrupt() {
+    const SERIAL_BASE: *mut u32 = (KERNEL_OFFSET + 0x18000000) as *mut u32;
+    const UART_CTRL_REG: usize = 3;
+    // Intr enable | rx reset | tx reset
+    const UART_IE: u32 = 0x13;
+    SERIAL_BASE.add(UART_CTRL_REG).write_volatile(UART_IE);
+}

kernel/src/arch/riscv32/interrupt.rs

@@ -74,7 +74,7 @@ pub extern "C" fn rust_trap(tf: &mut TrapFrame) {
 }
 
 fn external() {
-    #[cfg(feature = "board_u540")]
+    #[cfg(any(feature = "board_u540", feature = "board_rocket_chip"))]
     unsafe {
         super::board::handle_external_interrupt();
     }

kernel/src/arch/riscv32/memory.rs

@@ -92,7 +92,7 @@ fn remap_the_kernel(dtb: usize) {
         Linear::new(offset),
         "bss",
     );
-    // TODO: dtb on rocket chip
+    // dtb on rocket chip is embedded into kernel
     #[cfg(not(feature = "board_rocket_chip"))]
     ms.push(
         dtb,
@@ -133,6 +133,33 @@ fn remap_the_kernel(dtb: usize) {
         Linear::new(offset),
         "uart16550",
     );
+    // map PLIC for Rocket Chip
+    #[cfg(feature = "board_rocket_chip")]
+    ms.push(
+        KERNEL_OFFSET + 0x0C20_1000,
+        KERNEL_OFFSET + 0x0C20_1000 + PAGE_SIZE,
+        MemoryAttr::default(),
+        Linear::new(offset),
+        "plic2",
+    );
+    // map UART for Rocket Chip
+    #[cfg(feature = "board_rocket_chip")]
+    ms.push(
+        KERNEL_OFFSET + 0x18000000,
+        KERNEL_OFFSET + 0x18000000 + PAGE_SIZE,
+        MemoryAttr::default(),
+        Linear::new(-(KERNEL_OFFSET as isize + 0x18000000 - 0x60000000)),
+        "uartlite",
+    );
+    // map AXI INTC for Rocket Chip
+    #[cfg(feature = "board_rocket_chip")]
+    ms.push(
+        KERNEL_OFFSET + 0x19000000,
+        KERNEL_OFFSET + 0x19000000 + PAGE_SIZE,
+        MemoryAttr::default(),
+        Linear::new(-(KERNEL_OFFSET as isize + 0x19000000 - 0x61200000)),
+        "axi_intc",
+    );
     unsafe {
         ms.activate();
     }

kernel/src/arch/riscv32/mod.rs

@@ -1,7 +1,10 @@
 #[cfg(feature = "board_u540")]
 #[path = "board/u540/mod.rs"]
 mod board;
-#[cfg(not(feature = "board_u540"))]
+#[cfg(feature = "board_rocket_chip")]
+#[path = "board/rocket_chip/mod.rs"]
+mod board;
+#[cfg(not(any(feature = "board_u540", feature = "board_rocket_chip")))]
 #[path = "board/virt/mod.rs"]
 mod board;
 
@@ -23,10 +26,20 @@ use log::*;
 
 #[no_mangle]
 pub extern "C" fn rust_main(hartid: usize, device_tree_paddr: usize) -> ! {
-    let device_tree_vaddr = device_tree_paddr - MEMORY_OFFSET + KERNEL_OFFSET;
+    let mut device_tree_vaddr = device_tree_paddr - MEMORY_OFFSET + KERNEL_OFFSET;
 
     unsafe {
         cpu::set_cpu_id(hartid);
+
+    }
+
+    #[cfg(feature = "board_rocket_chip")]
+    {
+        extern "C" {
+            fn _dtb_start();
+            fn _dtb_end();
+        }
+        device_tree_vaddr = _dtb_start as usize;
     }
 
     if hartid != BOOT_HART_ID {
@@ -53,11 +66,10 @@ pub extern "C" fn rust_main(hartid: usize, device_tree_paddr: usize) -> ! {
     memory::init(device_tree_vaddr);
     timer::init();
     // FIXME: init driver on u540
-    #[cfg(not(any(feature = "board_u540", feature = "board_rocket_chip")))]
+    #[cfg(not(any(feature = "board_u540")))]
     crate::drivers::init(device_tree_vaddr);
     #[cfg(not(feature = "board_k210"))]
     unsafe {
-        #[cfg(not(feature = "board_rocket_chip"))]
         board::enable_serial_interrupt();
         board::init_external_interrupt();
     }
@@ -115,3 +127,5 @@ global_asm!(include_str!("boot/entry64.asm"));
 #[cfg(feature = "board_k210")]
 global_asm!(include_str!("boot/entry_k210.asm"));
 global_asm!(include_str!("boot/trap.asm"));
+#[cfg(feature = "board_rocket_chip")]
+global_asm!(include_str!("boot/dtb.gen.s"));

kernel/src/drivers/console/mod.rs

@@ -28,7 +28,7 @@ pub struct ConsoleChar {
 impl Default for ConsoleChar {
     fn default() -> Self {
         ConsoleChar {
-            ascii_char: 0,
+            ascii_char: b' ',
             attr: CharacterAttribute::default(),
         }
     }
@@ -152,7 +152,7 @@ impl<F: Font> Console<F> {
 
     fn new_line(&mut self) {
         let attr_blank = ConsoleChar {
-            ascii_char: 0,
+            ascii_char: b' ',
             attr: self.parser.char_attribute(),
         };
         for j in self.col..self.buf.num_col {

kernel/src/fs/stdio.rs

@@ -29,14 +29,7 @@ impl Stdin {
                 return c;
             }
         }
-        #[cfg(feature = "board_rocket_chip")]
+        #[cfg(not(feature = "board_k210"))]
-        loop {
-            let c = crate::arch::io::getchar();
-            if c != '\0' && c as u8 != 254 {
-                return c;
-            }
-        }
-        #[cfg(not(any(feature = "board_k210", feature = "board_rocket_chip")))]
         loop {
             let mut buf_lock = self.buf.lock();
             match buf_lock.pop_front() {
@@ -48,11 +41,6 @@ impl Stdin {
         }
     }
     pub fn can_read(&self) -> bool {
-        // Currently, rocket-chip implementation rely on htif interface, the serial interrupt DO
-        // NOT work, so return true always
-        #[cfg(feature = "board_rocket_chip")]
-        return true;
-        #[cfg(not(feature = "board_rocket_chip"))]
         return self.buf.lock().len() > 0;
     }
 }

kernel/src/util/escape_parser.rs

@@ -156,8 +156,12 @@ impl EscapeParser {
                     }
                     let csi = CSI::new(byte, &self.params);
                     if csi == CSI::SGR {
-                        for &param in self.params.iter() {
+                        if self.params.is_empty() {
-                            self.char_attr.apply_sgr(param);
+                            self.char_attr.apply_sgr(0);
+                        } else {
+                            for &param in self.params.iter() {
+                                self.char_attr.apply_sgr(param);
+                            }
                         }
                     }
                     self.status = ParseStatus::Text;

kernel/targets/aarch64.json

@@ -20,7 +20,7 @@
   },
   "llvm-target": "aarch64-unknown-none",
   "no-compiler-rt": true,
-  "features": "+a53,+strict-align,-neon",
+  "features": "+a53,+strict-align,-neon,-fp-armv8",
   "max-atomic-width": 128,
   "os": "none",
   "panic": "abort",