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https://github.com/rcore-os/rCore.git
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296 lines
6.1 KiB
ArmAsm
296 lines
6.1 KiB
ArmAsm
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// See LICENSE for license details.
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#include "mtrap.h"
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#include "bits.h"
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.data
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.align 6
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trap_table:
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#define BAD_TRAP_VECTOR 0
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.word bad_trap
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.word pmp_trap
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.word illegal_insn_trap
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.word bad_trap
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.word misaligned_load_trap
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.word pmp_trap
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.word misaligned_store_trap
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.word pmp_trap
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.word bad_trap
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.word mcall_trap
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.word bad_trap
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.word bad_trap
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.word bad_trap
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#define TRAP_FROM_MACHINE_MODE_VECTOR 13
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.word __trap_from_machine_mode
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.word bad_trap
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.word bad_trap
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.option norvc
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.section .text.init,"ax",@progbits
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.globl reset_vector
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reset_vector:
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j do_reset
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trap_vector:
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csrrw sp, mscratch, sp
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beqz sp, .Ltrap_from_machine_mode
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STORE a0, 10*REGBYTES(sp)
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STORE a1, 11*REGBYTES(sp)
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csrr a1, mcause
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bgez a1, .Lhandle_trap_in_machine_mode
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# This is an interrupt. Discard the mcause MSB and decode the rest.
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sll a1, a1, 1
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# Is it a machine timer interrupt?
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li a0, IRQ_M_TIMER * 2
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bne a0, a1, 1f
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# Yes. Simply clear MSIE and raise SSIP.
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li a0, MIP_MTIP
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csrc mie, a0
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li a0, MIP_STIP
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csrs mip, a0
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.Lmret:
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# Go back whence we came.
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LOAD a0, 10*REGBYTES(sp)
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LOAD a1, 11*REGBYTES(sp)
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csrrw sp, mscratch, sp
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mret
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1:
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# Is it an IPI?
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li a0, IRQ_M_SOFT * 2
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bne a0, a1, .Lbad_trap
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# Yes. First, clear the MIPI bit.
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LOAD a0, MENTRY_IPI_OFFSET(sp)
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sw x0, (a0)
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fence
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# Now, decode the cause(s).
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#ifdef __riscv_atomic
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addi a0, sp, MENTRY_IPI_PENDING_OFFSET
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amoswap.w a0, x0, (a0)
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#else
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lw a0, MENTRY_IPI_PENDING_OFFSET(a0)
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sw x0, MENTRY_IPI_PENDING_OFFSET(a0)
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#endif
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and a1, a0, IPI_SOFT
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beqz a1, 1f
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csrs mip, MIP_SSIP
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1:
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andi a1, a0, IPI_FENCE_I
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beqz a1, 1f
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fence.i
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1:
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andi a1, a0, IPI_SFENCE_VMA
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beqz a1, 1f
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sfence.vma
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1:
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j .Lmret
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.Lhandle_trap_in_machine_mode:
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# Preserve the registers. Compute the address of the trap handler.
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STORE ra, 1*REGBYTES(sp)
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STORE gp, 3*REGBYTES(sp)
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STORE tp, 4*REGBYTES(sp)
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STORE t0, 5*REGBYTES(sp)
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1:auipc t0, %pcrel_hi(trap_table) # t0 <- %hi(trap_table)
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STORE t1, 6*REGBYTES(sp)
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sll t1, a1, 2 # t1 <- mcause << 2
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STORE t2, 7*REGBYTES(sp)
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add t1, t0, t1 # t1 <- %hi(trap_table)[mcause]
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STORE s0, 8*REGBYTES(sp)
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LWU t1, %pcrel_lo(1b)(t1) # t1 <- trap_table[mcause]
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STORE s1, 9*REGBYTES(sp)
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mv a0, sp # a0 <- regs
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STORE a2,12*REGBYTES(sp)
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csrr a2, mepc # a2 <- mepc
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STORE a3,13*REGBYTES(sp)
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csrrw t0, mscratch, x0 # t0 <- user sp
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STORE a4,14*REGBYTES(sp)
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STORE a5,15*REGBYTES(sp)
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STORE a6,16*REGBYTES(sp)
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STORE a7,17*REGBYTES(sp)
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STORE s2,18*REGBYTES(sp)
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STORE s3,19*REGBYTES(sp)
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STORE s4,20*REGBYTES(sp)
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STORE s5,21*REGBYTES(sp)
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STORE s6,22*REGBYTES(sp)
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STORE s7,23*REGBYTES(sp)
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STORE s8,24*REGBYTES(sp)
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STORE s9,25*REGBYTES(sp)
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STORE s10,26*REGBYTES(sp)
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STORE s11,27*REGBYTES(sp)
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STORE t3,28*REGBYTES(sp)
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STORE t4,29*REGBYTES(sp)
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STORE t5,30*REGBYTES(sp)
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STORE t6,31*REGBYTES(sp)
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STORE t0, 2*REGBYTES(sp) # sp
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#ifndef __riscv_flen
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lw tp, (sp) # Move the emulated FCSR from x0's save slot into tp.
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#endif
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STORE x0, (sp) # Zero x0's save slot.
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# Invoke the handler.
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jalr t1
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#ifndef __riscv_flen
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sw tp, (sp) # Move the emulated FCSR from tp into x0's save slot.
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#endif
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restore_mscratch:
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# Restore mscratch, so future traps will know they didn't come from M-mode.
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csrw mscratch, sp
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restore_regs:
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# Restore all of the registers.
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LOAD ra, 1*REGBYTES(sp)
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LOAD gp, 3*REGBYTES(sp)
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LOAD tp, 4*REGBYTES(sp)
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LOAD t0, 5*REGBYTES(sp)
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LOAD t1, 6*REGBYTES(sp)
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LOAD t2, 7*REGBYTES(sp)
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LOAD s0, 8*REGBYTES(sp)
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LOAD s1, 9*REGBYTES(sp)
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LOAD a0,10*REGBYTES(sp)
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LOAD a1,11*REGBYTES(sp)
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LOAD a2,12*REGBYTES(sp)
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LOAD a3,13*REGBYTES(sp)
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LOAD a4,14*REGBYTES(sp)
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LOAD a5,15*REGBYTES(sp)
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LOAD a6,16*REGBYTES(sp)
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LOAD a7,17*REGBYTES(sp)
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LOAD s2,18*REGBYTES(sp)
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LOAD s3,19*REGBYTES(sp)
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LOAD s4,20*REGBYTES(sp)
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LOAD s5,21*REGBYTES(sp)
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LOAD s6,22*REGBYTES(sp)
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LOAD s7,23*REGBYTES(sp)
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LOAD s8,24*REGBYTES(sp)
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LOAD s9,25*REGBYTES(sp)
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LOAD s10,26*REGBYTES(sp)
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LOAD s11,27*REGBYTES(sp)
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LOAD t3,28*REGBYTES(sp)
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LOAD t4,29*REGBYTES(sp)
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LOAD t5,30*REGBYTES(sp)
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LOAD t6,31*REGBYTES(sp)
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LOAD sp, 2*REGBYTES(sp)
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mret
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.Ltrap_from_machine_mode:
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csrr sp, mscratch
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addi sp, sp, -INTEGER_CONTEXT_SIZE
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STORE a0,10*REGBYTES(sp)
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STORE a1,11*REGBYTES(sp)
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li a1, TRAP_FROM_MACHINE_MODE_VECTOR
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j .Lhandle_trap_in_machine_mode
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.Lbad_trap:
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li a1, BAD_TRAP_VECTOR
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j .Lhandle_trap_in_machine_mode
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.globl __redirect_trap
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__redirect_trap:
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# reset sp to top of M-mode stack
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li t0, MACHINE_STACK_SIZE
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add sp, sp, t0
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neg t0, t0
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and sp, sp, t0
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addi sp, sp, -MENTRY_FRAME_SIZE
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j restore_mscratch
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__trap_from_machine_mode:
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jal trap_from_machine_mode
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j restore_regs
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do_reset:
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li x1, 0
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li x2, 0
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li x3, 0
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li x4, 0
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li x5, 0
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li x6, 0
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li x7, 0
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li x8, 0
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li x9, 0
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// save a0 and a1; arguments from previous boot loader stage:
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// li x10, 0
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// li x11, 0
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li x12, 0
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li x13, 0
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li x14, 0
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li x15, 0
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li x16, 0
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li x17, 0
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li x18, 0
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li x19, 0
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li x20, 0
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li x21, 0
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li x22, 0
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li x23, 0
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li x24, 0
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li x25, 0
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li x26, 0
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li x27, 0
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li x28, 0
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li x29, 0
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li x30, 0
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li x31, 0
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csrw mscratch, x0
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# write mtvec and make sure it sticks
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la t0, trap_vector
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csrw mtvec, t0
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csrr t1, mtvec
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1:bne t0, t1, 1b
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la sp, stacks + RISCV_PGSIZE - MENTRY_FRAME_SIZE
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csrr a3, mhartid
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slli a2, a3, RISCV_PGSHIFT
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add sp, sp, a2
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# Boot on the first hart
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beqz a3, init_first_hart
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# set MSIE bit to receive IPI
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li a2, MIP_MSIP
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csrw mie, a2
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.LmultiHart:
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#if MAX_HARTS > 1
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# wait for an IPI to signal that it's safe to boot
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wfi
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# masked harts never start
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la a4, disabled_hart_mask
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LOAD a4, 0(a4)
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srl a4, a4, a3
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andi a4, a4, 1
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bnez a4, .LmultiHart
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# only start if mip is set
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csrr a2, mip
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andi a2, a2, MIP_MSIP
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beqz a2, .LmultiHart
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# make sure our hart id is within a valid range
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fence
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li a2, MAX_HARTS
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bltu a3, a2, init_other_hart
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#endif
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wfi
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j .LmultiHart
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.bss
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.align RISCV_PGSHIFT
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stacks:
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.skip RISCV_PGSIZE * MAX_HARTS
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