1
0
mirror of https://github.com/rcore-os/rCore.git synced 2024-11-25 17:33:28 +04:00
rCore/README.md

62 lines
2.3 KiB
Markdown
Raw Normal View History

2018-07-06 19:14:51 +04:00
# RustOS
2017-04-11 21:44:44 +04:00
2018-08-07 12:48:34 +04:00
[![Build Status](https://travis-ci.org/wangrunji0408/RustOS.svg?branch=master)](https://travis-ci.org/wangrunji0408/RustOS)
2018-07-06 19:14:51 +04:00
2018-11-19 21:29:44 +04:00
Rust version of THU [uCore OS](https://github.com/chyyuu/ucore_os_lab/).
Going to be the next generation teaching operating system.
2018-12-02 18:19:32 +04:00
Supported architectures: x86_64, RISCV32IMA(S/M), AArch64
2018-12-16 07:47:33 +04:00
Tested boards: QEMU, labeled-RISCV, Raspberry Pi 3B+
2018-07-06 19:14:51 +04:00
[Dev docs](https://rucore.gitbook.io/rust-os-docs/) (in Chinese)
2018-12-16 07:47:33 +04:00
![demo](./docs/2_OSLab/os2atc/demo.png)
2018-07-04 12:23:11 +04:00
## Summary
2018-11-19 21:29:44 +04:00
This is a project of THU courses:
* Operating System (2018 Spring)
* Comprehensive Experiment of Computer System (2018 Summer)
* Operating System Train (2018 Autumn)
2018-04-03 17:42:23 +04:00
2018-11-19 21:29:44 +04:00
Project wiki (internal access only): [OS](http://os.cs.tsinghua.edu.cn/oscourse/OS2018spring/projects/g11), [CECS](http://os.cs.tsinghua.edu.cn/oscourse/csproject2018/group05), [OST](http://os.cs.tsinghua.edu.cn/oscourse/OsTrain2018)
2017-04-11 21:44:44 +04:00
2018-11-19 21:29:44 +04:00
Reports (in Chinese): [docs](./docs)
2018-04-02 11:28:32 +04:00
2018-05-25 18:15:37 +04:00
2018-08-07 12:48:34 +04:00
The initial goal is to write a mini OS in Rust with multi-core support. More specifically, it would start from the post of the [Writing an OS in Rust](http://os.phil-opp.com) series, then reimplement [xv6-x86_64](https://github.com/jserv/xv6-x86_64) in Rust style.
2018-04-02 11:28:32 +04:00
2018-08-07 12:48:34 +04:00
In fact, it's more complicated than we expected to write an OS starting from scratch. So by the end of OS course, we only finished rewriting [ucore_os_lab](https://github.com/chyyuu/ucore_os_lab), without multi-core support. Then as a part of [CECS project](https://github.com/riscv-and-rust-and-decaf), we ported it from x86_64 to RISCV32I, and made it work on our FPGA CPU.
2017-04-11 21:44:44 +04:00
## Building
2018-08-07 12:48:34 +04:00
### Environment
2018-11-19 21:29:44 +04:00
* [Rust](https://www.rust-lang.org) toolchain at nightly
2018-09-19 16:43:49 +04:00
* Cargo tools: [cargo-xbuild](https://github.com/rust-osdev/cargo-xbuild), [bootimage](https://github.com/rust-osdev/bootimage)
* QEMU >= 2.12.0
* [RISCV64 GNU toolchain](https://www.sifive.com/products/tools/) (for riscv32)
2018-11-19 21:29:44 +04:00
* [AArch64 GNU toolchain](https://web.stanford.edu/class/cs140e/assignments/0-blinky/) (for aarch64)
2017-04-11 21:44:44 +04:00
2018-08-07 12:48:34 +04:00
### How to run
2018-09-19 16:43:49 +04:00
```bash
rustup component add rust-src
cargo install cargo-xbuild bootimage
```
2018-08-07 12:48:34 +04:00
```bash
2018-11-28 20:20:12 +04:00
git clone https://github.com/wangrunji0408/RustOS.git --recursive
2018-08-07 12:48:34 +04:00
cd RustOS/kernel
2018-11-19 21:29:44 +04:00
rustup override set nightly
make run arch=riscv32|x86_64|aarch64
2018-08-07 12:48:34 +04:00
```
2017-04-11 21:44:44 +04:00
## License
2018-04-02 11:28:32 +04:00
2017-04-11 21:44:44 +04:00
The source code is dual-licensed under MIT or the Apache License (Version 2.0).