diff --git a/risc_v/src/asm/boot.S b/risc_v/src/asm/boot.S
index f910dcd..b8976a5 100644
--- a/risc_v/src/asm/boot.S
+++ b/risc_v/src/asm/boot.S
@@ -96,7 +96,7 @@ _start:
 	sub		sp, sp, t0
 
 	# The parked harts will be put into machine mode with interrupts enabled.
-	li		t0, 0b11 << 11 | (1 << 7)
+	li		t0, 0b11 << 11 | (1 << 7) | (1 << 13)
 	csrw	mstatus, t0
 	# Allow for MSIP (Software interrupt). We will write the MSIP from hart #0 to
 	# awaken these parked harts.
diff --git a/risc_v/src/asm/trap.S b/risc_v/src/asm/trap.S
index dbb0298..ccb2e04 100644
--- a/risc_v/src/asm/trap.S
+++ b/risc_v/src/asm/trap.S
@@ -54,11 +54,24 @@ m_trap_vector:
 
 	# Restore the kernel trap frame into mscratch
 	csrw	mscratch, t5
-	# csrw	mie, zero
+
+	csrr	t1, mstatus
+	srli	t0, t1, 13
+	andi	t0, t0, 3
+
+	beqz	t0, 1f
+	# Save floating point registers
+	.set 	i, 0
+	.rept	32
+		save_fp	%i, t5
+		.set	i, i+1
+	.endr
+1:
 	# Get ready to go into Rust (trap.rs)
 	# We don't want to write into the user's stack or whomever
 	# messed with us here.
 	# csrw	mie, zero
+
 	csrr	a0, mepc
 	sd		a0, 520(t5)
 	csrr	a1, mtval
@@ -78,6 +91,17 @@ m_trap_vector:
 	# Now load the trap frame back into t6
 	csrr	t6, mscratch
 
+	csrr	t1, mstatus
+	srli	t0, t1, 13
+	andi	t0, t0, 3
+
+	beqz	t0, 1f
+	.set	i, 0
+	.rept	32
+		load_fp %i
+		.set i, i+1
+	.endr
+1:
 	# Restore all GP registers
 	.set	i, 1
 	.rept	31
@@ -108,7 +132,7 @@ switch_to_user:
 	# 1 << 7 is MPIE
 	# Since user mode is 00, we don't need to set anything
 	# in MPP (bits 12:11)
-	li		t0, 1 << 7 | 1 << 5
+	li		t0, 1 << 7 | 1 << 5 | 1 << 13
 	# Combine enable bits with mode bits.
 	slli	a3, a3, 11
 	or		t0, t0, a3
@@ -127,6 +151,17 @@ switch_to_user:
 	# A0 is the context frame, so we need to reload it back
 	# and mret so we can start running the program.
 	mv	t6, a0
+	csrr	t1, mstatus
+	srli	t0, t1, 13
+	andi	t0, t0, 3
+
+	beqz	t0, 1f
+	.set	i, 0
+	.rept	32
+		load_fp %i
+		.set i, i+1
+	.endr
+1:
 	.set	i, 1
 	.rept	31
 		load_gp %i, t6
diff --git a/risc_v/src/cpu.rs b/risc_v/src/cpu.rs
index 83d16a9..0240f98 100755
--- a/risc_v/src/cpu.rs
+++ b/risc_v/src/cpu.rs
@@ -63,6 +63,43 @@ pub enum Registers {
 	T6
 }
 
+// Floating point registers
+#[repr(usize)]
+pub enum FRegisters {
+	Ft0,
+	Ft1,
+	Ft2,
+	Ft3,
+	Ft4,
+	Ft5,
+	Ft6,
+	Ft7,
+	Fs0,
+	Fs1,
+	Fa0, /* 10 */
+	Fa1,
+	Fa2,
+	Fa3,
+	Fa4,
+	Fa5,
+	Fa6,
+	Fa7,
+	Fs2,
+	Fs3,
+	Fs4, /* 20 */
+	Fs5,
+	Fs6,
+	Fs7,
+	Fs8,
+	Fs9,
+	Fs10,
+	Fs11,
+	Ft8,
+	Ft9,
+	Ft10, /* 30 */
+	Ft11
+}
+
 /// The trap frame is set into a structure
 /// and packed into each hart's mscratch register.
 /// This allows for quick reference and full