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Merge pull request #6 from koutheir/patch-1

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Comments on assembly code in boot.S
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Stephen Marz 2019-10-06 13:38:37 -04:00 committed by GitHub
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risc_v/ch1/src/asm/boot.S
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@ -2,9 +2,17 @@
# bootloader for SoS
# Stephen Marz
# 8 February 2019
# Disable generation of compressed instructions.
.option norvc
# Define a .data section.
.section .data
# Define a .text.init section.
.section .text.init
# Execution starts here.
.global _start
_start:
# Any hardware threads (hart) that are not bootstrapping
@ -13,11 +21,15 @@ _start:
bnez t0, 3f
# SATP should be zero, but let's make sure
csrw satp, zero
# Disable linker instruction relaxation for the `la` instruction below.
# This disallows the assembler from assuming that `gp` is already initialized.
# This causes the value stored in `gp` to be calculated from `pc`.
.option push
.option norelax
la gp, _global_pointer
.option pop
# The BSS section is expected to be zero
# Set all bytes in the BSS section to zero.
la a0, _bss_start
la a1, _bss_end
bgeu a0, a1, 2f
@ -32,17 +44,27 @@ _start:
# csrw medeleg, t5
# csrw mideleg, t5
la sp, _stack
# We use mret here so that the mstatus register
# is properly updated.
# Setting `mstatus` register:
# 0b11 << 11: Machine's previous protection mode is 3 (MPP=3).
# 1 << 7 : Machine's previous interrupt-enable bit is 1 (MPIE=1).
# 1 << 3 : Machine's interrupt-enable bit is 1 (MIE=1).
li t0, (0b11 << 11) | (1 << 7) | (1 << 3)
csrw mstatus, t0
# Machine's exception program counter (MEPC) is set to `kmain`.
la t1, kmain
csrw mepc, t1
# Machine's trap vector base address is set to `asm_trap_vector`.
la t2, asm_trap_vector
csrw mtvec, t2
# Setting Machine's interrupt-enable bits (`mie` register):
# 1 << 3 : Machine's M-mode software interrupt-enable bit is 1 (MSIE=1).
# 1 << 7 : Machine's timer interrupt-enable bit is 1 (MTIE=1).
# 1 << 11: Machine's external interrupt-enable bit is 1 (MEIE=1).
li t3, (1 << 3) | (1 << 7) | (1 << 11)
csrw mie, t3
# Set the return address to infinitely wait for interrupts.
la ra, 4f
# We use mret here so that the mstatus register is properly updated.
mret
3: