2020-04-26 05:23:00 +04:00
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OUTPUT_ARCH( "riscv" )
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ENTRY( _start )
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MEMORY
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{
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ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 128M
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}
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PHDRS
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{
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text PT_LOAD;
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2020-04-26 16:33:49 +04:00
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rodata PT_LOAD;
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2020-04-26 05:23:00 +04:00
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data PT_LOAD;
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bss PT_LOAD;
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}
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SECTIONS
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{
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.text : {
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PROVIDE(_text_start = .);
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*(.text.init) *(.text .text.*)
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PROVIDE(_text_end = .);
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} >ram AT>ram :text
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PROVIDE(_global_pointer = .);
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.rodata : {
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PROVIDE(_rodata_start = .);
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*(.rodata .rodata.*)
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PROVIDE(_rodata_end = .);
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2020-04-26 16:33:49 +04:00
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} >ram AT>ram :rodata
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2020-04-26 05:23:00 +04:00
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.data : {
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PROVIDE(_data_start = .);
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*(.sdata .sdata.*) *(.data .data.*)
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PROVIDE(_data_end = .);
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} >ram AT>ram :data
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.bss :{
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PROVIDE(_bss_start = .);
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*(.sbss .sbss.*) *(.bss .bss.*)
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PROVIDE(_bss_end = .);
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} >ram AT>ram :bss
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PROVIDE(_memory_start = ORIGIN(ram));
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PROVIDE(_stack = _bss_end + 0x80000);
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PROVIDE(_memory_end = ORIGIN(ram) + LENGTH(ram));
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PROVIDE(_heap_start = _stack);
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PROVIDE(_heap_size = _memory_end - _stack);
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}
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