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rust/i2c: Use variants in init
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@ -57,8 +57,6 @@ impl<IF: I2C012> I2CImpl<IF> {
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impl<IF: I2C012> I2C for I2CImpl<IF> {
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impl<IF: I2C012> I2C for I2CImpl<IF> {
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fn init(&self, slave_address: u16, address_width: u32, i2c_clk: u32) {
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fn init(&self, slave_address: u16, address_width: u32, i2c_clk: u32) {
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assert!(address_width == 7 || address_width == 10);
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sysctl::clock_enable(IF::CLK);
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sysctl::clock_enable(IF::CLK);
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sysctl::clock_set_threshold(IF::DIV, 3);
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sysctl::clock_set_threshold(IF::DIV, 3);
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@ -67,13 +65,19 @@ impl<IF: I2C012> I2C for I2CImpl<IF> {
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let v_period_clk_cnt: u16 = v_period_clk_cnt.try_into().unwrap();
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let v_period_clk_cnt: u16 = v_period_clk_cnt.try_into().unwrap();
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let v_period_clk_cnt = cmp::max(v_period_clk_cnt, 1);
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let v_period_clk_cnt = cmp::max(v_period_clk_cnt, 1);
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use i2c0::con::{ADDR_SLAVE_WIDTHW,SPEEDW};
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let v_width = match address_width {
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7 => ADDR_SLAVE_WIDTHW::B7,
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10 => ADDR_SLAVE_WIDTHW::B10,
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_ => panic!("unsupported address width"),
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};
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unsafe {
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unsafe {
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self.i2c.enable.write(|w| w.bits(0));
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self.i2c.enable.write(|w| w.bits(0));
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self.i2c.con.write(|w| w.master_mode().bit(true)
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self.i2c.con.write(|w| w.master_mode().bit(true)
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.slave_disable().bit(true)
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.slave_disable().bit(true)
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.restart_en().bit(true)
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.restart_en().bit(true)
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.addr_slave_width().bit(address_width == 10) // TODO variant
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.addr_slave_width().variant(v_width)
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.speed().bits(1)); // TODO variant
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.speed().variant(SPEEDW::FAST));
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self.i2c.ss_scl_hcnt.write(|w| w.count().bits(v_period_clk_cnt));
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self.i2c.ss_scl_hcnt.write(|w| w.count().bits(v_period_clk_cnt));
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self.i2c.ss_scl_lcnt.write(|w| w.count().bits(v_period_clk_cnt));
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self.i2c.ss_scl_lcnt.write(|w| w.count().bits(v_period_clk_cnt));
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self.i2c.tar.write(|w| w.address().bits(slave_address));
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self.i2c.tar.write(|w| w.address().bits(slave_address));
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