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rust: k210-pac dependency bump

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This commit is contained in:
Wladimir J. van der Laan 2019-08-15 12:48:41 +00:00
parent b6b5d13b0c
commit 1990bff89f
7 changed files with 31 additions and 30 deletions
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1
rust/Cargo.toml
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@ -18,6 +18,7 @@ members = [
[patch.crates-io] [patch.crates-io]
k210-hal = { git = "https://github.com/riscv-rust/k210-hal.git", rev = "b83e843c19a2f0bc4eb7f56322ae844818709298" } k210-hal = { git = "https://github.com/riscv-rust/k210-hal.git", rev = "b83e843c19a2f0bc4eb7f56322ae844818709298" }
k210-pac = { git = "https://github.com/riscv-rust/k210-pac.git", rev = "91b421e17729b549566271a66ba19ce6fc205178" }
# cc-rs needs new release with PR #428 #429 #430 (will be 1.0.39, probably) # cc-rs needs new release with PR #428 #429 #430 (will be 1.0.39, probably)
cc = { git = "https://github.com/alexcrichton/cc-rs.git", rev = "13e04b1ec0ba8530c01f32ffafaeb70e6ad1c875" } cc = { git = "https://github.com/alexcrichton/cc-rs.git", rev = "13e04b1ec0ba8530c01f32ffafaeb70e6ad1c875" }

28
rust/k210-shared/src/soc/dmac.rs
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@ -1,7 +1,7 @@
//! DMAC peripheral //! DMAC peripheral
use k210_hal::pac; use k210_hal::pac;
use pac::dmac::channel::cfg::{TT_FCW,HS_SEL_SRCW}; use pac::dmac::channel::cfg::{TT_FC_A,HS_SEL_SRC_A};
use pac::dmac::channel::ctl::{SMSW}; use pac::dmac::channel::ctl::{SMS_A};
use crate::soc::sysctl; use crate::soc::sysctl;
@ -39,10 +39,10 @@ pub enum src_dst_select {
} }
pub use crate::soc::sysctl::dma_channel; pub use crate::soc::sysctl::dma_channel;
pub type master_number = pac::dmac::channel::ctl::SMSW; pub type master_number = pac::dmac::channel::ctl::SMS_A;
pub type address_increment = pac::dmac::channel::ctl::SINCW; pub type address_increment = pac::dmac::channel::ctl::SINC_A;
pub type burst_length = pac::dmac::channel::ctl::SRC_MSIZEW; pub type burst_length = pac::dmac::channel::ctl::SRC_MSIZE_A;
pub type transfer_width = pac::dmac::channel::ctl::SRC_TR_WIDTHW; pub type transfer_width = pac::dmac::channel::ctl::SRC_TR_WIDTH_A;
/** Return whether a specific address considered considered memory or peripheral */ /** Return whether a specific address considered considered memory or peripheral */
fn is_memory(address: u64) -> bool { fn is_memory(address: u64) -> bool {
@ -250,10 +250,10 @@ impl DMAC {
let src_is_mem = is_memory(src); let src_is_mem = is_memory(src);
let dest_is_mem = is_memory(dest); let dest_is_mem = is_memory(dest);
let flow_control = match (src_is_mem, dest_is_mem) { let flow_control = match (src_is_mem, dest_is_mem) {
(false, false) => TT_FCW::PRF2PRF_DMA, (false, false) => TT_FC_A::PRF2PRF_DMA,
(true, false) => TT_FCW::MEM2PRF_DMA, (true, false) => TT_FC_A::MEM2PRF_DMA,
(false, true) => TT_FCW::PRF2MEM_DMA, (false, true) => TT_FC_A::PRF2MEM_DMA,
(true, true) => TT_FCW::MEM2MEM_DMA, (true, true) => TT_FC_A::MEM2MEM_DMA,
}; };
/* /*
@ -262,8 +262,8 @@ impl DMAC {
*/ */
ch.cfg.modify(|_,w| ch.cfg.modify(|_,w|
w.tt_fc().variant(flow_control) w.tt_fc().variant(flow_control)
.hs_sel_src().variant(if src_is_mem { HS_SEL_SRCW::SOFTWARE } else { HS_SEL_SRCW::HARDWARE } ) .hs_sel_src().variant(if src_is_mem { HS_SEL_SRC_A::SOFTWARE } else { HS_SEL_SRC_A::HARDWARE } )
.hs_sel_dst().variant(if dest_is_mem { HS_SEL_SRCW::SOFTWARE } else { HS_SEL_SRCW::HARDWARE } ) .hs_sel_dst().variant(if dest_is_mem { HS_SEL_SRC_A::SOFTWARE } else { HS_SEL_SRC_A::HARDWARE } )
// Note: from SVD: "Assign a hardware handshaking interface to source of channel", // Note: from SVD: "Assign a hardware handshaking interface to source of channel",
// these are set using sysctl::dma_select; this configuration seems to indicate // these are set using sysctl::dma_select; this configuration seems to indicate
// that in principle, it's possible to use a different source and destination // that in principle, it's possible to use a different source and destination
@ -279,8 +279,8 @@ impl DMAC {
ch.dar.write(|w| w.bits(dest)); ch.dar.write(|w| w.bits(dest));
ch.ctl.modify(|_,w| ch.ctl.modify(|_,w|
w.sms().variant(SMSW::AXI_MASTER_1) w.sms().variant(SMS_A::AXI_MASTER_1)
.dms().variant(SMSW::AXI_MASTER_2) .dms().variant(SMS_A::AXI_MASTER_2)
/* master select */ /* master select */
.sinc().variant(src_inc) .sinc().variant(src_inc)
.dinc().variant(dest_inc) .dinc().variant(dest_inc)

10
rust/k210-shared/src/soc/dvp.rs
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@ -37,7 +37,7 @@ pub struct DVP {
} }
/** Borrow image_format enum from pac */ /** Borrow image_format enum from pac */
pub use dvp::dvp_cfg::FORMATW as image_format; pub use dvp::dvp_cfg::FORMAT_A as image_format;
impl DVP { impl DVP {
/** Set SCCB clock to a safe and deterministic value (as low as possible) */ /** Set SCCB clock to a safe and deterministic value (as low as possible) */
@ -82,7 +82,7 @@ impl DVP {
/** Set a register value through SCCB */ /** Set a register value through SCCB */
pub fn sccb_send_data(&self, dev_addr: u8, reg_addr: u16, reg_data: u8) { pub fn sccb_send_data(&self, dev_addr: u8, reg_addr: u16, reg_data: u8) {
use dvp::sccb_cfg::BYTE_NUMW::*; use dvp::sccb_cfg::BYTE_NUM_A::*;
unsafe { unsafe {
match self.sccb_addr_len { match self.sccb_addr_len {
sccb_addr_len::W8 => { sccb_addr_len::W8 => {
@ -106,7 +106,7 @@ impl DVP {
/** Receive register value through SCCB */ /** Receive register value through SCCB */
pub fn sccb_receive_data(&self, dev_addr: u8, reg_addr: u16) -> u8 { pub fn sccb_receive_data(&self, dev_addr: u8, reg_addr: u16) -> u8 {
// Write read request // Write read request
use dvp::sccb_cfg::BYTE_NUMW::*; use dvp::sccb_cfg::BYTE_NUM_A::*;
unsafe { unsafe {
match self.sccb_addr_len { match self.sccb_addr_len {
sccb_addr_len::W8 => { sccb_addr_len::W8 => {
@ -186,11 +186,11 @@ impl DVP {
pub fn set_image_size(&self, burst_mode: bool, width: u16, height: u16) { pub fn set_image_size(&self, burst_mode: bool, width: u16, height: u16) {
let burst_num = if burst_mode { let burst_num = if burst_mode {
self.dvp.dvp_cfg.modify(|_,w| w.burst_size_4beats().set_bit()); self.dvp.dvp_cfg.modify(|_,w| w.burst_size_4beats().set_bit());
self.dvp.axi.modify(|_,w| w.gm_mlen().variant(dvp::axi::GM_MLENW::BYTE4)); self.dvp.axi.modify(|_,w| w.gm_mlen().variant(dvp::axi::GM_MLEN_A::BYTE4));
width / 8 / 4 width / 8 / 4
} else { } else {
self.dvp.dvp_cfg.modify(|_,w| w.burst_size_4beats().clear_bit()); self.dvp.dvp_cfg.modify(|_,w| w.burst_size_4beats().clear_bit());
self.dvp.axi.modify(|_,w| w.gm_mlen().variant(dvp::axi::GM_MLENW::BYTE1)); self.dvp.axi.modify(|_,w| w.gm_mlen().variant(dvp::axi::GM_MLEN_A::BYTE1));
width / 8 / 1 width / 8 / 1
}; };
assert!(burst_num < 256); assert!(burst_num < 256);

8
rust/k210-shared/src/soc/i2c.rs
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@ -58,10 +58,10 @@ impl<IF: I2CExt> I2C for I2CImpl<IF> {
let v_period_clk_cnt: u16 = v_period_clk_cnt.try_into().unwrap(); let v_period_clk_cnt: u16 = v_period_clk_cnt.try_into().unwrap();
let v_period_clk_cnt = cmp::max(v_period_clk_cnt, 1); let v_period_clk_cnt = cmp::max(v_period_clk_cnt, 1);
use i2c0::con::{ADDR_SLAVE_WIDTHW,SPEEDW}; use i2c0::con::{ADDR_SLAVE_WIDTH_A,SPEED_A};
let v_width = match address_width { let v_width = match address_width {
7 => ADDR_SLAVE_WIDTHW::B7, 7 => ADDR_SLAVE_WIDTH_A::B7,
10 => ADDR_SLAVE_WIDTHW::B10, 10 => ADDR_SLAVE_WIDTH_A::B10,
_ => panic!("unsupported address width"), _ => panic!("unsupported address width"),
}; };
unsafe { unsafe {
@ -70,7 +70,7 @@ impl<IF: I2CExt> I2C for I2CImpl<IF> {
.slave_disable().bit(true) .slave_disable().bit(true)
.restart_en().bit(true) .restart_en().bit(true)
.addr_slave_width().variant(v_width) .addr_slave_width().variant(v_width)
.speed().variant(SPEEDW::FAST)); .speed().variant(SPEED_A::FAST));
self.i2c.ss_scl_hcnt.write(|w| w.count().bits(v_period_clk_cnt)); self.i2c.ss_scl_hcnt.write(|w| w.count().bits(v_period_clk_cnt));
self.i2c.ss_scl_lcnt.write(|w| w.count().bits(v_period_clk_cnt)); self.i2c.ss_scl_lcnt.write(|w| w.count().bits(v_period_clk_cnt));
self.i2c.tar.write(|w| w.address().bits(slave_address)); self.i2c.tar.write(|w| w.address().bits(slave_address));

4
rust/k210-shared/src/soc/pwm.rs
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@ -64,7 +64,7 @@ impl<TIMER: TimerExt> PWM for PWMImpl<TIMER> {
/** Start a PWM channel */ /** Start a PWM channel */
fn start(&self, ch: Channel) { fn start(&self, ch: Channel) {
unsafe { unsafe {
use pac::timer0::channel::control::MODEW; use pac::timer0::channel::control::MODE_A;
// set a deterministic value for load counts // set a deterministic value for load counts
self.timer.channel[ch.idx()].load_count.write(|w| w.bits(1)); self.timer.channel[ch.idx()].load_count.write(|w| w.bits(1));
@ -73,7 +73,7 @@ impl<TIMER: TimerExt> PWM for PWMImpl<TIMER> {
self.timer.channel[ch.idx()].control.write( self.timer.channel[ch.idx()].control.write(
|w| w.interrupt().set_bit() |w| w.interrupt().set_bit()
.pwm_enable().set_bit() .pwm_enable().set_bit()
.mode().variant(MODEW::USER) .mode().variant(MODE_A::USER)
.enable().set_bit()); .enable().set_bit());
} }
} }

8
rust/k210-shared/src/soc/spi.rs
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@ -52,13 +52,13 @@ pub struct SPIImpl<IF> {
} }
/** Borrow work mode from pac */ /** Borrow work mode from pac */
pub use ctrlr0::WORK_MODEW as work_mode; pub use ctrlr0::WORK_MODE_A as work_mode;
/** Borrow frame format from pac */ /** Borrow frame format from pac */
pub use ctrlr0::FRAME_FORMATW as frame_format; pub use ctrlr0::FRAME_FORMAT_A as frame_format;
/** Borrow aitm from pac */ /** Borrow aitm from pac */
pub use spi_ctrlr0::AITMW as aitm; pub use spi_ctrlr0::AITM_A as aitm;
/** Borrow tmod from pac */ /** Borrow tmod from pac */
pub use ctrlr0::TMODW as tmod; pub use ctrlr0::TMOD_A as tmod;
pub trait SPI { pub trait SPI {
fn configure( fn configure(

2
rust/k210-shared/src/soc/sysctl.rs
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@ -179,7 +179,7 @@ impl dma_channel {
pub fn idx(self) -> usize { self as usize } pub fn idx(self) -> usize { self as usize }
} }
pub type dma_select = pac::sysctl::dma_sel0::DMA_SEL0W; pub type dma_select = pac::sysctl::dma_sel0::DMA_SEL0_A;
fn clock_bus_en(clock: clock, en: bool) { fn clock_bus_en(clock: clock, en: bool) {
/* /*