2019-05-04 16:00:08 +04:00
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OTP layout
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==========
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Some random notes about the layout of the Kendryte K210 OTP memory.
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There is some on-board One-Time Programmable Memory, which is used
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to configure the boot sequence as used by the boot ROM. A part of it is pre-written
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in the factory.
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The total size seems to be 16384 (0x4000) bytes.
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```
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Ofs Type Description
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----------------------------------------------------
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0000 u32 "ROXM" (0x4d584f52) magic value
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0004 u16 Size of "boot patch" program
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0006 u8[sz] Program data to be copied
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3d91 u8[11] Looks like a production run identifier (ASCII)
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3d9c u32? Serial number? Differs per board instance
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3da0 u16 ?
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3da2 u16 ?
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3da4 u16 ?
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3da6 u16 ?
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2019-05-07 21:35:16 +04:00
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3db0 u8[32] Expected SHA256 hash of firmware
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2019-05-04 16:00:08 +04:00
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3fd0 u8[16] 2 bits per entry, for 64 entries
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3fe0 u8[16] 2 bits per entry, for 64 entries
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3ff0 u8[16] Causes read errors. Might be write-only area for encryption key.
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```
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- The "boot patch" program is copied to SRAM at address 0x805f8000 at boot and
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executed. I think it's meant to be a vector to fix issues in the ROM without
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having to modify the chip.
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- You can read the OTP of your board using the `otp_dump` tool in this
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repository. Note that the OTP contains a serial number (at least
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0x3d9c..0x3d9f seem to differ between boards) so it'd be wise to treat the
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output as privacy-sensitive.
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- My intuition is that the areas at 0x3fd0 and 0x3fe0 are bit fields that specify
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which parts of the OTP have been written and which have not.
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- Be careful: any writing to the OTP (if possible at all, I don't know, there
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are some routines in the ROM that look like they might do this but haven't
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tried !) might brick your chip unrecoverably.
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2019-05-07 21:35:16 +04:00
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Fuses A
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-------
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OTP register `0x68` has some bits that affect the boot process.
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These might be one-time programmable fuses.
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The following bits are known:
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```
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Bit Description
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-------- ------------------------------------------------------------
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1 If set, allow entering ISP even if Fuses B bit 7 disallows it, force normal boot
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```
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Fuses B
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-------
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OTP registers `0xbc` (=bits 32..63) and `0xb8` (=bits 0..31) affect the boot process.
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These might be one-time programmable fuses.
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```
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Bit Description
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-------- ------------------------------------------------------------
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0 checked in unreached ROM code, specific use unknown
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7 disallow entering ISP
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8 skip decryption of firmware
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9 check SHA256 against OTP 0x3db0
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61 if bit 62 not set: if set, boot only SPI0 (external), else only SPI3 (internal)
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62 try booting SPI0 (external) flash first then SPI3 (internal) flash
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63 determines kind of boot (sets higher frequencies-might be the TURBO MODE mentioned in the datasheet)
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```
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