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39 lines
1.7 KiB
Markdown
39 lines
1.7 KiB
Markdown
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Notes on K210 MMU
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=================
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The K210 has a MMU based on the RISC-V privileged spec 1.9.1.
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This means that:
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- The `sfence.vm` (bit pattern `0x10400073`) instruction should be used to
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synchronize updates to the page tables with current execution, not
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`sfence.vma` (bit pattern `0x12000073`). See spec section 4.2.1.
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- The `sptbr` CSR (`0x180`, Supervisor Page-Table Base Register) specifies the
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current root page table. In the newer spec this register is called `satp`
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and is completely different.
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- In spec v1.9.1, `sstatus.SUM` is still `PUM` which has opposite meaning.
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- To switch on paging, set the `VM` bitfield (offset 24:28) of `mstatus` to `Sv39` (9).
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Also, [reportedly](https://www.reddit.com/r/RISCV/comments/fguddz/linux011_with_mmu_for_k210_riscv/fk9otke/) interrupts do not work as expected in S mode, making that
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mode more or less useless. Only M and U mode can be used in practice.
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To access paged memory from M mode, the `MPRV` bit in `mstatus` can be set, with `MPP` set to
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`0` (U mode). From the spec (section 3.1.9):
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> The MPRV bit modifies the privilege level at which loads and stores execute. When MPRV=0,
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> translation and protection behave as normal. When MPRV=1, data memory addresses are trans-
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> lated and protected as though the current privilege mode were set to MPP. Instruction address-
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> translation and protection are unaffected
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Examples
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---------
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There is a little bit of example code for using the MMU on the K210:
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- [https://github.com/lizhirui/K210-Linux0.11.git](Linux0.11 with MMU)
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- [https://github.com/44670/libk9/blob/develop/k9/CacheEngine.c](CacheEngine.c)
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- [https://github.com/oscourse-tsinghua/rcore_plus/issues/34#issuecomment-485145060](Some notes on porting a rust-based OS to K210)
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