mirror of
https://github.com/helix-editor/helix.git
synced 2024-12-18 22:11:55 +04:00
deploy: 548f04fe26
This commit is contained in:
parent
a7afd271da
commit
d4609cd929
@ -393,6 +393,7 @@ Languages</a> guide for more language configuration information.</p>
|
|||||||
<tr><td>uxntal</td><td>✓</td><td></td><td></td><td></td></tr>
|
<tr><td>uxntal</td><td>✓</td><td></td><td></td><td></td></tr>
|
||||||
<tr><td>v</td><td>✓</td><td>✓</td><td>✓</td><td><code>v-analyzer</code></td></tr>
|
<tr><td>v</td><td>✓</td><td>✓</td><td>✓</td><td><code>v-analyzer</code></td></tr>
|
||||||
<tr><td>vala</td><td>✓</td><td>✓</td><td></td><td><code>vala-language-server</code></td></tr>
|
<tr><td>vala</td><td>✓</td><td>✓</td><td></td><td><code>vala-language-server</code></td></tr>
|
||||||
|
<tr><td>vento</td><td>✓</td><td></td><td></td><td></td></tr>
|
||||||
<tr><td>verilog</td><td>✓</td><td>✓</td><td></td><td><code>svlangserver</code></td></tr>
|
<tr><td>verilog</td><td>✓</td><td>✓</td><td></td><td><code>svlangserver</code></td></tr>
|
||||||
<tr><td>vhdl</td><td>✓</td><td></td><td></td><td><code>vhdl_ls</code></td></tr>
|
<tr><td>vhdl</td><td>✓</td><td></td><td></td><td><code>vhdl_ls</code></td></tr>
|
||||||
<tr><td>vhs</td><td>✓</td><td></td><td></td><td></td></tr>
|
<tr><td>vhs</td><td>✓</td><td></td><td></td><td></td></tr>
|
||||||
|
@ -1402,6 +1402,7 @@ Languages</a> guide for more language configuration information.</p>
|
|||||||
<tr><td>uxntal</td><td>✓</td><td></td><td></td><td></td></tr>
|
<tr><td>uxntal</td><td>✓</td><td></td><td></td><td></td></tr>
|
||||||
<tr><td>v</td><td>✓</td><td>✓</td><td>✓</td><td><code>v-analyzer</code></td></tr>
|
<tr><td>v</td><td>✓</td><td>✓</td><td>✓</td><td><code>v-analyzer</code></td></tr>
|
||||||
<tr><td>vala</td><td>✓</td><td>✓</td><td></td><td><code>vala-language-server</code></td></tr>
|
<tr><td>vala</td><td>✓</td><td>✓</td><td></td><td><code>vala-language-server</code></td></tr>
|
||||||
|
<tr><td>vento</td><td>✓</td><td></td><td></td><td></td></tr>
|
||||||
<tr><td>verilog</td><td>✓</td><td>✓</td><td></td><td><code>svlangserver</code></td></tr>
|
<tr><td>verilog</td><td>✓</td><td>✓</td><td></td><td><code>svlangserver</code></td></tr>
|
||||||
<tr><td>vhdl</td><td>✓</td><td></td><td></td><td><code>vhdl_ls</code></td></tr>
|
<tr><td>vhdl</td><td>✓</td><td></td><td></td><td><code>vhdl_ls</code></td></tr>
|
||||||
<tr><td>vhs</td><td>✓</td><td></td><td></td><td></td></tr>
|
<tr><td>vhs</td><td>✓</td><td></td><td></td><td></td></tr>
|
||||||
|
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
Loading…
Reference in New Issue
Block a user